On Thu, Jul 03, 2014 at 05:33:03PM -0400, Rodrigo Vivi wrote:
> From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>
> On g33, the documentation states
>
> "HWS_PGA:
> Format = Bits 28:12 of graphics memory address (bits 31:29 MBZ)."
>
> which translates to that the address of the HWS must be below 256MiB,
> which is conveniently the mappable aperture.
>
> This also appears to be true (but not documented as so) for gen4 and
> gen5. To generalise we force it into the low mappable region for all
> non-LLC platforms. If we locate the HWS at the top of the GTT the
> machine will hard hang during boot (fails on pnv, gm45, ilk and byt,
> but works on snb, ivb, hsw).
>
> v2: Add comments to explain why use PIN_MAPPABLE even though we have
> no intention of mapping the object. (Ville)
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2faef26..f49a3dd 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1331,6 +1331,7 @@ static int init_status_page(struct intel_engine_cs *ring)
> struct drm_i915_gem_object *obj;
>
> if ((obj = ring->status_page.obj) == NULL) {
> + unsigned flags;
> int ret;
>
> obj = i915_gem_alloc_object(ring->dev, 4096);
> @@ -1343,7 +1344,20 @@ static int init_status_page(struct intel_engine_cs *ring)
> if (ret)
> goto err_unref;
>
> - ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
> + flags = 0;
> + if (!HAS_LLC(ring->dev))
> + /* On g33, we cannot place HWS above 256MiB, so
> + * restrict its pinning to the low mappable arena.
> + * Though this restriction is not documented for
> + * gen4, gen5, or byt, they also behave similarly
> + * and hang if the HWS is placed at the top of the
> + * GTT. To generalise, it appears that all !llc
> + * platforms have issues with us placing the HWS
> + * above the mappable region (even though we never
> + * actualy map it).
> + */
> + flags |= PIN_MAPPABLE;
> + ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
> if (ret) {
> err_unref:
> drm_gem_object_unreference(&obj->base);
> --
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
