2014-07-07 18:23 GMT-03:00 Daniel Vetter <daniel@xxxxxxxx>: > On Fri, Jul 04, 2014 at 11:50:29AM -0300, Paulo Zanoni wrote: >> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> >> >> If we enable unclaimed register reporting on Gen 8, we will discover >> that the IRQ registers for pipes B and C are also on the power well, >> so writes to them when the power well is disabled result in unclaimed >> register errors. >> >> Also, hsw_power_well_post_enable() already takes care of re-enabling >> them once the power well is enabled. >> >> Testcase: igt/pm_rpm/rte >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > > Hm, shouldn't we split this into only setting up pipe A here and the pipe > B stuff once we fire up the power well? > No because these functions might be called when the power wells are already enabled. > I just want to avoid duplicating logic all over the place ... > -Daniel > >> --- >> drivers/gpu/drm/i915/i915_irq.c | 11 ++++++++--- >> 1 file changed, 8 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> index 1c1ec22..2e116e9d 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.c >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> @@ -3193,7 +3193,9 @@ static void gen8_irq_reset(struct drm_device *dev) >> gen8_gt_irq_reset(dev_priv); >> >> for_each_pipe(pipe) >> - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); >> + if (intel_display_power_enabled(dev_priv, >> + POWER_DOMAIN_PIPE(pipe))) >> + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); >> >> GEN5_IRQ_RESET(GEN8_DE_PORT_); >> GEN5_IRQ_RESET(GEN8_DE_MISC_); >> @@ -3526,8 +3528,11 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) >> dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; >> >> for_each_pipe(pipe) >> - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], >> - de_pipe_enables); >> + if (intel_display_power_enabled(dev_priv, >> + POWER_DOMAIN_PIPE(pipe))) >> + GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, >> + dev_priv->de_irq_mask[pipe], >> + de_pipe_enables); >> >> GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); >> } >> -- >> 2.0.0 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
