On Wed, Jul 02, 2014 at 10:51:23AM -0700, Jesse Barnes wrote: > On Thu, 26 Jun 2014 18:23:58 +0100 > John.C.Harrison@xxxxxxxxx wrote: > > > From: John Harrison <John.C.Harrison@xxxxxxxxx> > > > > There is a workaround for a hardware bug when reading the seqno from the status > > page. The bug does not exist on VLV however, the workaround was still being > > applied. > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 279488a..bad5db0 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -1960,7 +1960,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > > ring->irq_put = gen6_ring_put_irq; > > } > > ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; > > - ring->get_seqno = gen6_ring_get_seqno; > > + if (IS_VALLEYVIEW(dev)) > > + ring->get_seqno = ring_get_seqno; > > + else > > + ring->get_seqno = gen6_ring_get_seqno; > > ring->set_seqno = ring_set_seqno; > > ring->semaphore.sync_to = gen6_ring_sync; > > ring->semaphore.signal = gen6_signal; > > Assuming this has been well tested: > Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> I have my doubts ... the seqno race is fairly hard to reproduce really and needs some serious beating. Also highly timing dependent. My best guess is that Oscar's irq handling race fixes fixed the underlying bug on gen6+, so I think we should instead dare to rip out this w/a completely and see what happens. Doing this on gen6+ will at least give us serious amounts of test coverage. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
