[PATCH] perf

[Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>]

---
 drivers/gpu/drm/i915/i915_perf.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7345b507a9dc..3741f69bc36f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -46,6 +46,8 @@ static void rings_sample(struct drm_i915_private *dev_priv)
 	if (!gpu_active(dev_priv))
 		return;
 
+	intel_runtime_pm_get(dev_priv);
+
 	if (dev_priv->info.gen >= 6)
 		gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 
@@ -99,6 +101,8 @@ static void rings_sample(struct drm_i915_private *dev_priv)
 
 	if (dev_priv->info.gen >= 6)
 		gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+
+	intel_runtime_pm_put(dev_priv);
 }
 
 static void frequency_sample(struct drm_i915_private *dev_priv)
@@ -107,6 +111,7 @@ static void frequency_sample(struct drm_i915_private *dev_priv)
 		u64 val;
 
 		if (gpu_active(dev_priv)) {
+			intel_runtime_pm_get(dev_priv);
 			if (dev_priv->info.is_valleyview) {
 				mutex_lock(&dev_priv->rps.hw_lock);
 				val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
@@ -120,6 +125,7 @@ static void frequency_sample(struct drm_i915_private *dev_priv)
 					val = (val & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
 				val *= GT_FREQUENCY_MULTIPLIER;
 			}
+			intel_runtime_pm_put(dev_priv);
 		} else {
 			val = dev_priv->rps.cur_freq; /* minor white lie to save power */
 			if (dev_priv->info.is_valleyview)
@@ -422,6 +428,7 @@ static inline u64 calc_residency(struct drm_i915_private *dev_priv, const u32 re
 {
 	if (dev_priv->info.gen >= 6) {
 		u64 val, units = 128, div = 100000;
+		intel_runtime_pm_get(dev_priv);
 		if (dev_priv->info.is_valleyview) {
 			u32 clock;
 
@@ -436,6 +443,7 @@ static inline u64 calc_residency(struct drm_i915_private *dev_priv, const u32 re
 			div *= 1000;
 		}
 		val = I915_READ_NOTRACE(reg);
+		intel_runtime_pm_put(dev_priv);
 		val *= units;
 		return DIV_ROUND_UP_ULL(val, div);
 	} else
@@ -448,10 +456,12 @@ static inline u64 read_statistic(struct drm_i915_private *dev_priv,
 	const u32 reg = 0x2310 + 8 *statistic;
 	u32 high, low;
 
+	intel_runtime_pm_get(dev_priv);
 	do {
 		high = I915_READ_NOTRACE(reg + 4);
 		low = I915_READ_NOTRACE(reg);
 	} while (high != I915_READ_NOTRACE(reg + 4));
+	intel_runtime_pm_put(dev_priv);
 
 	return (u64)high << 32 | low;
 }
-- 
2.0.1

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