On Thu, Jul 03, 2014 at 05:33:05PM -0400, Rodrigo Vivi wrote: > From: Ben Widawsky <benjamin.widawsky@xxxxxxxxx> > > The PDPs seem to get screwed up otherwise, specifically PDP0. I am not > really clear why this is required, it just works with full PPGTT. > > v2: Only do it for gen8, to limit regression potential > > v3: Fix the bugzilla links > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938 > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index 633e318..61b60b6 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -573,6 +573,9 @@ mi_set_context(struct intel_engine_cs *ring, > else > intel_ring_emit(ring, MI_NOOP); > > + if (INTEL_INFO(ring->dev)->gen == 8) > + hw_flags |= MI_FORCE_RESTORE; > + > intel_ring_emit(ring, MI_NOOP); > intel_ring_emit(ring, MI_SET_CONTEXT); > intel_ring_emit(ring, Ville had a good point on this patch wrt to note setting both MI_FORCE_RESTORE, and MI_RESTORE_INHIBIT (though it seems to cause no problems). I think also with some of the do_switch() cleanups recently submitted, this one may no longer be necessary - not sure. -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
