On Wed, 02 Jul 2014, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > Adapt the macro so that we can pass either the struct drm_device or the > struct drm_i915_private pointers and get the answer we want. Polymorphism?! :o > text data bss dec hex filename > 8138307 1234176 679936 10052419 996343 vmlinux.before > 8137591 1234176 679936 10051703 996077 vmlinux.after > > 700 bytes of code saving and peace of mind. Just don't look at the > macro. I did. I think I need to get new glasses now. I haven't yet decided whether this is really hideous or really cool. Maybe both. BR, Jani. > --- > drivers/gpu/drm/i915/i915_drv.h | 55 ++++++++++++++++++----------------- > drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-- > drivers/gpu/drm/i915/i915_irq.c | 16 +++++----- > drivers/gpu/drm/i915/i915_sysfs.c | 11 ++++--- > drivers/gpu/drm/i915/intel_display.c | 54 +++++++++++++++++----------------- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_i2c.c | 8 ++--- > drivers/gpu/drm/i915/intel_lvds.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 10 +++---- > drivers/gpu/drm/i915/intel_uncore.c | 20 ++++++------- > 11 files changed, 93 insertions(+), 91 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 7838b298048c..1781889e65f0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1937,51 +1937,54 @@ struct drm_i915_cmd_table { > int count; > }; > > -#define INTEL_INFO(dev) (&to_i915(dev)->info) > +#define __I915__(ptr) ((sizeof(*(ptr)) == sizeof(struct drm_i915_private)) ? (struct drm_i915_private *)(ptr) : to_i915((struct drm_device *)ptr)) > +#define __DRM__(ptr) ((sizeof(*(ptr)) == sizeof(struct drm_i915_private)) ? ((struct drm_i915_private *)(ptr))->dev : (struct drm_device *)(ptr)) > +#define INTEL_INFO(dev) (&__I915__(dev)->info) > +#define INTEL_DEVICE(dev) (__DRM__(dev)->pdev->device) > > -#define IS_I830(dev) ((dev)->pdev->device == 0x3577) > -#define IS_845G(dev) ((dev)->pdev->device == 0x2562) > +#define IS_I830(dev) (INTEL_DEVICE(dev) == 0x3577) > +#define IS_845G(dev) (INTEL_DEVICE(dev) == 0x2562) > #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) > -#define IS_I865G(dev) ((dev)->pdev->device == 0x2572) > +#define IS_I865G(dev) (INTEL_DEVICE(dev) == 0x2572) > #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) > -#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) > -#define IS_I945G(dev) ((dev)->pdev->device == 0x2772) > +#define IS_I915GM(dev) (INTEL_DEVICE(dev) == 0x2592) > +#define IS_I945G(dev) (INTEL_DEVICE(dev) == 0x2772) > #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) > #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) > #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) > -#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) > +#define IS_GM45(dev) (INTEL_DEVICE(dev) == 0x2A42) > #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) > -#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) > -#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) > +#define IS_PINEVIEW_G(dev) (INTEL_DEVICE(dev) == 0xa001) > +#define IS_PINEVIEW_M(dev) (INTEL_DEVICE(dev) == 0xa011) > #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) > #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) > -#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) > +#define IS_IRONLAKE_M(dev) (INTEL_DEVICE(dev) == 0x0046) > #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) > -#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ > - (dev)->pdev->device == 0x0152 || \ > - (dev)->pdev->device == 0x015a) > -#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ > - (dev)->pdev->device == 0x0106 || \ > - (dev)->pdev->device == 0x010A) > +#define IS_IVB_GT1(dev) (INTEL_DEVICE(dev) == 0x0156 || \ > + INTEL_DEVICE(dev) == 0x0152 || \ > + INTEL_DEVICE(dev) == 0x015a) > +#define IS_SNB_GT1(dev) (INTEL_DEVICE(dev) == 0x0102 || \ > + INTEL_DEVICE(dev) == 0x0106 || \ > + INTEL_DEVICE(dev) == 0x010A) > #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) > #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) > #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) > #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) > #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ > - ((dev)->pdev->device & 0xFF00) == 0x0C00) > + (INTEL_DEVICE(dev) & 0xFF00) == 0x0C00) > #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ > - (((dev)->pdev->device & 0xf) == 0x2 || \ > - ((dev)->pdev->device & 0xf) == 0x6 || \ > - ((dev)->pdev->device & 0xf) == 0xe)) > + ((INTEL_DEVICE(dev) & 0xf) == 0x2 || \ > + (INTEL_DEVICE(dev) & 0xf) == 0x6 || \ > + (INTEL_DEVICE(dev) & 0xf) == 0xe)) > #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ > - ((dev)->pdev->device & 0xFF00) == 0x0A00) > + (INTEL_DEVICE(dev) & 0xFF00) == 0x0A00) > #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) > #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ > - ((dev)->pdev->device & 0x00F0) == 0x0020) > + (INTEL_DEVICE(dev) & 0x00F0) == 0x0020) > /* ULX machines are also considered ULT. */ > -#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \ > - (dev)->pdev->device == 0x0A1E) > +#define IS_HSW_ULX(dev) (INTEL_DEVICE(dev) == 0x0A0E || \ > + INTEL_DEVICE(dev) == 0x0A1E) > #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) > > /* > @@ -2009,7 +2012,7 @@ struct drm_i915_cmd_table { > #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) > #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) > #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ > - to_i915(dev)->ellc_size) > + __I915__(dev)->ellc_size) > #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) > > #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 5) > @@ -2062,7 +2065,7 @@ struct drm_i915_cmd_table { > #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 > #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 > > -#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) > +#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) > #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) > #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) > #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index f1581a4af7a7..1d5459316129 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -578,7 +578,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv, > } > > /* Cannot access snooped pages through the aperture */ > - if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) > + if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) > goto unwind; > > dst->page_count = num_pages; > @@ -929,7 +929,7 @@ static void i915_gem_record_rings(struct drm_device *dev, > request->ctx->vm : > &dev_priv->gtt.base); > > - if (HAS_BROKEN_CS_TLB(dev_priv->dev)) > + if (HAS_BROKEN_CS_TLB(dev_priv)) > error->ring[i].wa_batchbuffer = > i915_error_ggtt_object_create(dev_priv, > ring->scratch.obj); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 0edc97febf7b..a659f9cb513f 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -680,7 +680,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, > { > u32 enable_mask; > > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, > status_mask); > else > @@ -694,7 +694,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, > { > u32 enable_mask; > > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, > status_mask); > else > @@ -1260,7 +1260,7 @@ static void gen6_pm_rps_work(struct work_struct *work) > spin_lock_irq(&dev_priv->irq_lock); > pm_iir = dev_priv->rps.pm_iir; > dev_priv->rps.pm_iir = 0; > - if (IS_BROADWELL(dev_priv->dev)) > + if (IS_BROADWELL(dev_priv)) > bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > else { > /* Make sure not to corrupt PMIMR state used by ringbuffer */ > @@ -1282,7 +1282,7 @@ static void gen6_pm_rps_work(struct work_struct *work) > adj *= 2; > else { > /* CHV needs even encode values */ > - adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; > + adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; > } > new_delay = dev_priv->rps.cur_freq + adj; > > @@ -1303,7 +1303,7 @@ static void gen6_pm_rps_work(struct work_struct *work) > adj *= 2; > else { > /* CHV needs even encode values */ > - adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; > + adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; > } > new_delay = dev_priv->rps.cur_freq + adj; > } else { /* unknown event */ > @@ -1319,7 +1319,7 @@ static void gen6_pm_rps_work(struct work_struct *work) > > dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; > > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > valleyview_set_rps(dev_priv->dev, new_delay); > else > gen6_set_rps(dev_priv->dev, new_delay); > @@ -1738,7 +1738,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) > queue_work(dev_priv->wq, &dev_priv->rps.work); > } > > - if (HAS_VEBOX(dev_priv->dev)) { > + if (HAS_VEBOX(dev_priv)) { > if (pm_iir & PM_VEBOX_USER_INTERRUPT) > notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); > > @@ -2780,7 +2780,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr) > struct intel_engine_cs *signaller; > int i; > > - if (INTEL_INFO(dev_priv->dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > /* > * FIXME: gen8 semaphore support - currently we don't emit > * semaphores on bdw anyway, but this needs to be addressed when > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c > index 86ce39aad0ff..1f3902ae26e6 100644 > --- a/drivers/gpu/drm/i915/i915_sysfs.c > +++ b/drivers/gpu/drm/i915/i915_sysfs.c > @@ -266,7 +266,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, > intel_runtime_pm_get(dev_priv); > > mutex_lock(&dev_priv->rps.hw_lock); > - if (IS_VALLEYVIEW(dev_priv->dev)) { > + if (IS_VALLEYVIEW(dev_priv)) { > u32 freq; > freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff); > @@ -301,7 +301,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > > mutex_lock(&dev_priv->rps.hw_lock); > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); > else > ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; > @@ -328,7 +328,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, > > mutex_lock(&dev_priv->rps.hw_lock); > > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > val = vlv_freq_opcode(dev_priv, val); > else > val /= GT_FREQUENCY_MULTIPLIER; > @@ -366,14 +366,13 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, > static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) > { > struct drm_minor *minor = dev_to_drm_minor(kdev); > - struct drm_device *dev = minor->dev; > - struct drm_i915_private *dev_priv = dev->dev_private; > + struct drm_i915_private *dev_priv = to_i915(minor->dev); > int ret; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > > mutex_lock(&dev_priv->rps.hw_lock); > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); > else > ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 812b6a516145..69d6bfd7016d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1003,7 +1003,7 @@ bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, > { > u32 bit; > > - if (HAS_PCH_IBX(dev_priv->dev)) { > + if (HAS_PCH_IBX(dev_priv)) { > switch (port->port) { > case PORT_B: > bit = SDE_PORTB_HOTPLUG; > @@ -1094,7 +1094,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, > bool cur_state; > struct intel_dpll_hw_state hw_state; > > - if (HAS_PCH_LPT(dev_priv->dev)) { > + if (HAS_PCH_LPT(dev_priv)) { > DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); > return; > } > @@ -1118,7 +1118,7 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv, > enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, > pipe); > > - if (HAS_DDI(dev_priv->dev)) { > + if (HAS_DDI(dev_priv)) { > /* DDI does not have a specific FDI_TX register */ > reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); > val = I915_READ(reg); > @@ -1159,11 +1159,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, > u32 val; > > /* ILK FDI PLL is always enabled */ > - if (INTEL_INFO(dev_priv->dev)->gen == 5) > + if (INTEL_INFO(dev_priv)->gen == 5) > return; > > /* On Haswell, DDI ports are responsible for the FDI PLL setup */ > - if (HAS_DDI(dev_priv->dev)) > + if (HAS_DDI(dev_priv)) > return; > > reg = FDI_TX_CTL(pipe); > @@ -1194,7 +1194,7 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv, > enum pipe panel_pipe = PIPE_A; > bool locked = true; > > - if (HAS_PCH_SPLIT(dev_priv->dev)) { > + if (HAS_PCH_SPLIT(dev_priv)) { > pp_reg = PCH_PP_CONTROL; > lvds_reg = PCH_LVDS; > } else { > @@ -1343,7 +1343,7 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) > u32 val; > bool enabled; > > - WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); > + WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); > > val = I915_READ(PCH_DREF_CONTROL); > enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | > @@ -1372,12 +1372,12 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, > if ((val & DP_PORT_EN) == 0) > return false; > > - if (HAS_PCH_CPT(dev_priv->dev)) { > + if (HAS_PCH_CPT(dev_priv)) { > u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); > u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); > if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) > return false; > - } else if (IS_CHERRYVIEW(dev_priv->dev)) { > + } else if (IS_CHERRYVIEW(dev_priv)) { > if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) > return false; > } else { > @@ -1393,10 +1393,10 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, > if ((val & SDVO_ENABLE) == 0) > return false; > > - if (HAS_PCH_CPT(dev_priv->dev)) { > + if (HAS_PCH_CPT(dev_priv)) { > if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) > return false; > - } else if (IS_CHERRYVIEW(dev_priv->dev)) { > + } else if (IS_CHERRYVIEW(dev_priv)) { > if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) > return false; > } else { > @@ -1412,7 +1412,7 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, > if ((val & LVDS_PORT_EN) == 0) > return false; > > - if (HAS_PCH_CPT(dev_priv->dev)) { > + if (HAS_PCH_CPT(dev_priv)) { > if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) > return false; > } else { > @@ -1427,7 +1427,7 @@ static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, > { > if ((val & ADPA_DAC_ENABLE) == 0) > return false; > - if (HAS_PCH_CPT(dev_priv->dev)) { > + if (HAS_PCH_CPT(dev_priv)) { > if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) > return false; > } else { > @@ -1445,7 +1445,7 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, > "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", > reg, pipe_name(pipe)); > > - WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 > + WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 > && (val & DP_PIPEB_SELECT), > "IBX PCH dp port still using transcoder B\n"); > } > @@ -1458,7 +1458,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, > "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", > reg, pipe_name(pipe)); > > - WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 > + WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 > && (val & SDVO_PIPE_B_SELECT), > "IBX PCH hdmi port still using transcoder B\n"); > } > @@ -1571,10 +1571,10 @@ static void vlv_enable_pll(struct intel_crtc *crtc) > assert_pipe_disabled(dev_priv, crtc->pipe); > > /* No really, not for ILK+ */ > - BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); > + BUG_ON(!IS_VALLEYVIEW(dev_priv)); > > /* PLL is protected by panel, make sure we can write it */ > - if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) > + if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) > assert_panel_unlocked(dev_priv, crtc->pipe); > > I915_WRITE(reg, dpll); > @@ -1609,7 +1609,7 @@ static void chv_enable_pll(struct intel_crtc *crtc) > > assert_pipe_disabled(dev_priv, crtc->pipe); > > - BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); > + BUG_ON(!IS_CHERRYVIEW(dev_priv)); > > mutex_lock(&dev_priv->dpio_lock); > > @@ -1907,7 +1907,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, > val = I915_READ(reg); > pipeconf_val = I915_READ(PIPECONF(pipe)); > > - if (HAS_PCH_IBX(dev_priv->dev)) { > + if (HAS_PCH_IBX(dev_priv)) { > /* > * make the BPC in transcoder be consistent with > * that in pipeconf reg. > @@ -1918,7 +1918,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, > > val &= ~TRANS_INTERLACE_MASK; > if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) > - if (HAS_PCH_IBX(dev_priv->dev) && > + if (HAS_PCH_IBX(dev_priv) && > intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) > val |= TRANS_LEGACY_INTERLACED_ILK; > else > @@ -1937,7 +1937,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, > u32 val, pipeconf_val; > > /* PCH only available on ILK+ */ > - BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); > + BUG_ON(INTEL_INFO(dev_priv)->gen < 5); > > /* FDI must be feeding us bits for PCH ports */ > assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); > @@ -2031,7 +2031,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > assert_cursor_disabled(dev_priv, pipe); > assert_sprites_disabled(dev_priv, pipe); > > - if (HAS_PCH_LPT(dev_priv->dev)) > + if (HAS_PCH_LPT(dev_priv)) > pch_transcoder = TRANSCODER_A; > else > pch_transcoder = pipe; > @@ -2041,7 +2041,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > * a plane. On ILK+ the pipe PLLs are integrated, so we don't > * need the check. > */ > - if (!HAS_PCH_SPLIT(dev_priv->dev)) > + if (!HAS_PCH_SPLIT(dev_priv)) > if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) > assert_dsi_pll_enabled(dev_priv); > else > @@ -3711,7 +3711,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) > intel_put_shared_dpll(crtc); > } > > - if (HAS_PCH_IBX(dev_priv->dev)) { > + if (HAS_PCH_IBX(dev_priv)) { > /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ > i = (enum intel_dpll_id) crtc->pipe; > pll = &dev_priv->shared_dplls[i]; > @@ -3902,7 +3902,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) > if (!crtc->enabled || !intel_crtc->active) > return; > > - if (!HAS_PCH_SPLIT(dev_priv->dev)) { > + if (!HAS_PCH_SPLIT(dev_priv)) { > if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) > assert_dsi_pll_enabled(dev_priv); > else > @@ -7330,7 +7330,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, > > ironlake_get_fdi_m_n_config(crtc, pipe_config); > > - if (HAS_PCH_IBX(dev_priv->dev)) { > + if (HAS_PCH_IBX(dev_priv)) { > pipe_config->shared_dpll = > (enum intel_dpll_id) crtc->pipe; > } else { > @@ -13349,7 +13349,7 @@ intel_display_capture_error_state(struct drm_device *dev) > } > > error->num_transcoders = INTEL_INFO(dev)->num_pipes; > - if (HAS_DDI(dev_priv->dev)) > + if (HAS_DDI(dev_priv)) > error->num_transcoders++; /* Account for eDP. */ > > for (i = 0; i < error->num_transcoders; i++) { > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index ebc9a2a86280..15bba4a62115 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1591,7 +1591,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, > dotclock = intel_dotclock_calculate(pipe_config->port_clock, > &pipe_config->dp_m_n); > > - if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) > + if (HAS_PCH_SPLIT(dev_priv) && port != PORT_A) > ironlake_check_encoder_dotclock(pipe_config, dotclock); > > pipe_config->adjusted_mode.crtc_clock = dotclock; > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 24224131ebf1..bebb795e5a8a 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -738,7 +738,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, > else > dotclock = pipe_config->port_clock; > > - if (HAS_PCH_SPLIT(dev_priv->dev)) > + if (HAS_PCH_SPLIT(dev_priv)) > ironlake_check_encoder_dotclock(pipe_config, dotclock); > > pipe_config->adjusted_mode.crtc_clock = dotclock; > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index d33b61d0dd33..f0eab13fdccd 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -84,7 +84,7 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv) > { > int vco, gmbus_freq = 0, cdclk_div; > > - BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); > + BUG_ON(!IS_VALLEYVIEW(dev_priv)); > > vco = valleyview_get_vco(dev_priv); > > @@ -126,7 +126,7 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) > u32 val; > > /* When using bit bashing for I2C, this bit needs to be set to 1 */ > - if (!IS_PINEVIEW(dev_priv->dev)) > + if (!IS_PINEVIEW(dev_priv)) > return; > > val = I915_READ(DSPCLK_GATE_D); > @@ -268,7 +268,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv, > u32 gmbus2 = 0; > DEFINE_WAIT(wait); > > - if (!HAS_GMBUS_IRQ(dev_priv->dev)) > + if (!HAS_GMBUS_IRQ(dev_priv)) > gmbus4_irq_en = 0; > > /* Important: The hw handles only the first bit, so set only one! Since > @@ -305,7 +305,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) > > #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) > > - if (!HAS_GMBUS_IRQ(dev_priv->dev)) > + if (!HAS_GMBUS_IRQ(dev_priv)) > return wait_for(C, 10); > > /* Important: The hw handles only the first bit, so set only one! */ > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c > index 4d29a83fd163..cddf721a263d 100644 > --- a/drivers/gpu/drm/i915/intel_lvds.c > +++ b/drivers/gpu/drm/i915/intel_lvds.c > @@ -113,7 +113,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, > > dotclock = pipe_config->port_clock; > > - if (HAS_PCH_SPLIT(dev_priv->dev)) > + if (HAS_PCH_SPLIT(dev_priv)) > ironlake_check_encoder_dotclock(pipe_config, dotclock); > > pipe_config->adjusted_mode.crtc_clock = dotclock; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 36ca3f0457d0..7005ea3595e2 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3153,10 +3153,10 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) > /* IVB and SNB hard hangs on looping batchbuffer > * if GEN6_PM_UP_EI_EXPIRED is masked. > */ > - if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) > + if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) > mask |= GEN6_PM_RP_UP_EI_EXPIRED; > > - if (IS_GEN8(dev_priv->dev)) > + if (IS_GEN8(dev_priv)) > mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; > > return ~mask; > @@ -6392,13 +6392,13 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) > * The enabling order will be from lower to higher indexed wells, > * the disabling order is reversed. > */ > - if (IS_HASWELL(dev_priv->dev)) { > + if (IS_HASWELL(dev_priv)) { > set_power_wells(power_domains, hsw_power_wells); > hsw_pwr = power_domains; > - } else if (IS_BROADWELL(dev_priv->dev)) { > + } else if (IS_BROADWELL(dev_priv)) { > set_power_wells(power_domains, bdw_power_wells); > hsw_pwr = power_domains; > - } else if (IS_VALLEYVIEW(dev_priv->dev)) { > + } else if (IS_VALLEYVIEW(dev_priv)) { > set_power_wells(power_domains, vlv_power_wells); > } else { > set_power_wells(power_domains, i9xx_always_on_power_well); > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 993042d10165..7487dadfb6f7 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -43,7 +43,7 @@ > static void > assert_device_not_suspended(struct drm_i915_private *dev_priv) > { > - WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, > + WARN(HAS_RUNTIME_PM(dev_priv) && dev_priv->pm.suspended, > "Device suspended\n"); > } > > @@ -51,7 +51,7 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > { > u32 gt_thread_status_mask; > > - if (IS_HASWELL(dev_priv->dev)) > + if (IS_HASWELL(dev_priv)) > gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; > else > gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; > @@ -101,7 +101,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, > { > u32 forcewake_ack; > > - if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) > + if (IS_HASWELL(dev_priv) || IS_GEN8(dev_priv)) > forcewake_ack = FORCEWAKE_ACK_HSW; > else > forcewake_ack = FORCEWAKE_MT_ACK; > @@ -120,7 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, > DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); > > /* WaRsForcewakeWaitTC0:ivb,hsw */ > - if (INTEL_INFO(dev_priv->dev)->gen < 8) > + if (INTEL_INFO(dev_priv)->gen < 8) > __gen6_gt_wait_for_thread_c0(dev_priv); > } > > @@ -150,7 +150,7 @@ static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, > /* something from same cacheline, but !FORCEWAKE_MT */ > __raw_posting_read(dev_priv, ECOBUS); > > - if (IS_GEN7(dev_priv->dev)) > + if (IS_GEN7(dev_priv)) > gen6_gt_check_fifodbg(dev_priv); > } > > @@ -160,7 +160,7 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > > /* On VLV, FIFO will be shared by both SW and HW. > * So, we need to read the FREE_ENTRIES everytime */ > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > dev_priv->uncore.fifo_count = > __raw_i915_read32(dev_priv, GTFIFOCTL) & > GT_FIFO_FREE_ENTRIES_MASK; > @@ -231,7 +231,7 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, > } > > /* WaRsForcewakeWaitTC0:vlv */ > - if (!IS_CHERRYVIEW(dev_priv->dev)) > + if (!IS_CHERRYVIEW(dev_priv)) > __gen6_gt_wait_for_thread_c0(dev_priv); > } > > @@ -252,7 +252,7 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, > > /* something from same cacheline, but !FORCEWAKE_VLV */ > __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); > - if (!IS_CHERRYVIEW(dev_priv->dev)) > + if (!IS_CHERRYVIEW(dev_priv)) > gen6_gt_check_fifodbg(dev_priv); > } > > @@ -409,7 +409,7 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) > intel_runtime_pm_get(dev_priv); > > /* Redirect to VLV specific routine */ > - if (IS_VALLEYVIEW(dev_priv->dev)) > + if (IS_VALLEYVIEW(dev_priv)) > return vlv_force_wake_get(dev_priv, fw_engine); > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); > @@ -429,7 +429,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) > return; > > /* Redirect to VLV specific routine */ > - if (IS_VALLEYVIEW(dev_priv->dev)) { > + if (IS_VALLEYVIEW(dev_priv)) { > vlv_force_wake_put(dev_priv, fw_engine); > goto out; > } > -- > 2.0.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx