If the display power well has been disabled, the display audio controller divider values EM4 MVALUE and EM5 NVALUE will have been lost. Notify the BIOS about CDCLK change through opregion to make it reprogram the values when the audio driver requests the power well. Otherwise the audio playback speed may be wrong. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=74861 Reported-by: Neil Shepperd <nshepperd@xxxxxxxxx> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> --- NOTE: This will *not* yet fix the referenced bug; this is currently for Broadwell only. --- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a90fdbd30edf..b1cbb6f4ec06 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6237,6 +6237,17 @@ int i915_request_power_well(void) dev_priv = container_of(hsw_pwr, struct drm_i915_private, power_domains); intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); + + /* + * If the display power well has been disabled, the display audio + * controller divider values EM4 MVALUE and EM5 NVALUE will have been + * lost. Notify the BIOS about CDCLK change through opregion to make it + * reprogram the values. Otherwise the audio playback speed will be + * wrong. + */ + intel_opregion_notify_cdclk(dev_priv->dev, + intel_ddi_get_cdclk_freq(dev_priv)); + return 0; } EXPORT_SYMBOL_GPL(i915_request_power_well); -- 2.0.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
