2014-06-25 16:01 GMT-03:00 Imre Deak <imre.deak@xxxxxxxxx>:
> From: Daniel Vetter <daniel.vetter@xxxxxxxx>
>
> All the other checks also check hw state, so checking our software
> refcounts for the plls looks a bit odd. Also this will simplify the
> conversion over to the shared dpll framework, which itself has massive
> amounts of checks to make sure that we never leave a display pll
> enabled when we shouldn't.
>
> So after that conversion we should stil have a good enough coverage of
> asserts for entering pc8/runtime pm on hsw/bdw.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 065984d..2442a88 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7322,7 +7322,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> - struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
> struct intel_crtc *crtc;
>
> for_each_intel_crtc(dev, crtc)
> @@ -7330,9 +7329,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> pipe_name(crtc->pipe));
>
> WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
> - WARN(plls->spll_refcount, "SPLL enabled\n");
> - WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
> - WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
> + WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> + WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> + WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
> WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> "CPU PWM1 enabled\n");
> --
> 1.8.4
>
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--
Paulo Zanoni
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