On Fri, 13 Jun 2014 13:37:50 +0300
ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Depending on the HPLL frequency one of the supported cdclk frquencies is
> either 320MHz or 333MHz. Figure out which one it is to accurately pick
> the minimal required cdclk. This would also avoid a warning from the
> cdclk code where it compares the actual cdclk read out from the hardware
> with a value that was calculated using valleyview_calc_cdclk().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 61d7ea2..1f3985f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4509,19 +4509,22 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> int max_pixclk)
> {
> + int vco = valleyview_get_vco(dev_priv);
> + int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
> +
> /*
> * Really only a few cases to deal with, as only 4 CDclks are supported:
> * 200MHz
> * 267MHz
> - * 320MHz
> + * 320/333MHz (depends on HPLL freq)
> * 400MHz
> * So we check to see whether we're above 90% of the lower bin and
> * adjust if needed.
> */
> - if (max_pixclk > 320000*9/10)
> + if (max_pixclk > freq_320*9/10)
> return 400000;
> else if (max_pixclk > 266667*9/10)
> - return 320000;
> + return freq_320;
> else
> return 266667;
> /* Looks like the 200MHz CDclk freq doesn't work on some configs */
Looks good. This doc searching has been fun.
Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
--
Jesse Barnes, Intel Open Source Technology Center
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