On Tue, Jun 24, 2014 at 06:51:39PM +0530, Shobhit Kumar wrote:
> For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
> during the DSI enable sequence
>
> Causing WARN dump otherwise in dpio_reads
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx>
Yeah, the DPIO power wells might be down when enabling a DSI display so
we shouldn't go poking at DPIO registers.
But please add a !IS_CHERRYVIEW check there also, and then you can add:
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Looks like I need to split up chv_update_pll() in a similar fasion.
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fa77557..2fa7152 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4629,7 +4629,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->active)
> return;
>
> - vlv_prepare_pll(intel_crtc);
> + is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
> +
> + if (!is_dsi)
> + vlv_prepare_pll(intel_crtc);
>
> /* Set up the display plane register */
> dspcntr = DISPPLANE_GAMMA_ENABLE;
> @@ -4663,8 +4666,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> if (encoder->pre_pll_enable)
> encoder->pre_pll_enable(encoder);
>
> - is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
> -
> if (!is_dsi) {
> if (IS_CHERRYVIEW(dev))
> chv_enable_pll(intel_crtc);
> --
> 1.9.1
>
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--
Ville Syrjälä
Intel OTC
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