On Mon, Jun 16, 2014 at 08:59:04PM +0530, sourab.gupta@xxxxxxxxx wrote: > From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > This patch adds support for clearing buffer objects via blitter > engines. This is particularly useful for clearing out the memory > from stolen region. > > testcase: igt/gem_create2 > > Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx> This doesn't look like it'll work on gen8. -- Damien > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/i915_drv.h | 3 + > drivers/gpu/drm/i915/i915_gem_exec.c | 120 +++++++++++++++++++++++++++++++++++ > 3 files changed, 124 insertions(+) > create mode 100644 drivers/gpu/drm/i915/i915_gem_exec.c > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index cad1683..a18f7e5 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -22,6 +22,7 @@ i915-y += i915_cmd_parser.o \ > i915_gem_debug.o \ > i915_gem_dmabuf.o \ > i915_gem_evict.o \ > + i915_gem_exec.o \ > i915_gem_execbuffer.o \ > i915_gem_gtt.o \ > i915_gem.o \ > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 64d520f..0cdd4d7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2425,6 +2425,9 @@ int __must_check i915_gem_evict_something(struct drm_device *dev, > int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); > int i915_gem_evict_everything(struct drm_device *dev); > > +/* i915_gem_exec.c */ > +int i915_gem_exec_clear_object(struct drm_i915_gem_object *obj); > + > /* belongs in i915_gem_gtt.h */ > static inline void i915_gem_chipset_flush(struct drm_device *dev) > { > diff --git a/drivers/gpu/drm/i915/i915_gem_exec.c b/drivers/gpu/drm/i915/i915_gem_exec.c > new file mode 100644 > index 0000000..374f1e1 > --- /dev/null > +++ b/drivers/gpu/drm/i915/i915_gem_exec.c > @@ -0,0 +1,120 @@ > +/* > + * Copyright © 2013 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS > + * IN THE SOFTWARE. > + * > + * Authors: > + * Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > + * > + */ > + > +#include <drm/drmP.h> > +#include <drm/i915_drm.h> > +#include "i915_drv.h" > + > +#define COLOR_BLT_CMD (2<<29 | 0x40<<22) > +#define BLT_WRITE_ALPHA (1<<21) > +#define BLT_WRITE_RGB (1<<20) > +#define BLT_WRITE_RGBA (BLT_WRITE_RGB|BLT_WRITE_ALPHA) > + > +#define BPP_8 0 > +#define BPP_16 (1<<24) > +#define BPP_32 (1<<25 | 1<<24) > + > +#define ROP_FILL_COPY (0xf0 << 16) > + > +static int i915_gem_exec_flush_object(struct drm_i915_gem_object *obj, > + struct intel_engine_cs *ring) > +{ > + int ret; > + > + ret = i915_gem_object_sync(obj, ring); > + if (ret) > + return ret; > + > + if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) { > + if (i915_gem_clflush_object(obj, false)) > + i915_gem_chipset_flush(obj->base.dev); > + obj->base.write_domain &= ~I915_GEM_DOMAIN_CPU; > + } > + if (obj->base.write_domain & I915_GEM_DOMAIN_GTT) { > + wmb(); > + obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; > + } > + > + return intel_ring_invalidate_all_caches(ring); > +} > + > +static void i915_gem_exec_dirty_object(struct drm_i915_gem_object *obj, > + struct intel_engine_cs *ring) > +{ > + obj->fenced_gpu_access = false; > + obj->base.read_domains = I915_GEM_DOMAIN_RENDER; > + obj->base.write_domain = I915_GEM_DOMAIN_RENDER; > + i915_vma_move_to_active(i915_gem_obj_to_ggtt(obj), ring); > + obj->last_write_seqno = intel_ring_get_seqno(ring); > + obj->dirty = 1; > + > + ring->gpu_caches_dirty = true; > +} > + > +int i915_gem_exec_clear_object(struct drm_i915_gem_object *obj) > +{ > + struct drm_device *dev = obj->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_engine_cs *ring; > + int ret; > + > + lockdep_assert_held(&dev->struct_mutex); > + > + ring = &dev_priv->ring[HAS_BLT(dev) ? BCS : RCS]; > + > + ret = i915_gem_obj_ggtt_pin(obj, 0, 0); > + if (ret) > + return ret; > + > + if (obj->tiling_mode && INTEL_INFO(dev)->gen <= 3) { > + ret = i915_gem_object_put_fence(obj); > + if (ret) > + goto unpin; > + } > + > + ret = i915_gem_exec_flush_object(obj, ring); > + if (ret) > + goto unpin; > + > + ret = intel_ring_begin(ring, 6); > + if (ret) > + goto unpin; > + > + intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA | (5-2)); > + intel_ring_emit(ring, BPP_32 | ROP_FILL_COPY | PAGE_SIZE); > + intel_ring_emit(ring, obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE); > + intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj)); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, MI_NOOP); > + > + __intel_ring_advance(ring); > + i915_gem_exec_dirty_object(obj, ring); > + > +unpin: > + i915_gem_object_ggtt_unpin(obj); > + return ret; > +} > -- > 1.8.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx