On Thu, Jun 12, 2014 at 11:20:36AM +0300, Ville Syrjälä wrote: > On Tue, Jun 10, 2014 at 04:26:34PM -0700, Tom.O'Rourke@xxxxxxxxx wrote: > > From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx> > > > > Correct a merge mishap in commit e4443e459ccf43f2c139358400365fd6a839d40d. > > > > Wa*:chv belongs in cherryview_enable_rps, not gen8_enable_rps. > > > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx> > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Queued for -next, thanks for the patch. -Daniel > > > --- > > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 18f0ba0..c6e893b 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3520,15 +3520,11 @@ static void gen8_enable_rps(struct drm_device *dev) > > > > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > > > > - /* WaDisablePwrmtrEvent:chv (pre-production hw) */ > > - I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); > > - I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); > > - > > /* 5: Enable RPS */ > > I915_WRITE(GEN6_RP_CONTROL, > > GEN6_RP_MEDIA_TURBO | > > GEN6_RP_MEDIA_HW_NORMAL_MODE | > > - GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ > > + GEN6_RP_MEDIA_IS_GFX | > > GEN6_RP_ENABLE | > > GEN6_RP_UP_BUSY_AVG | > > GEN6_RP_DOWN_IDLE_AVG); > > @@ -4022,10 +4018,14 @@ static void cherryview_enable_rps(struct drm_device *dev) > > > > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > > > > + /* WaDisablePwrmtrEvent:chv (pre-production hw) */ > > + I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); > > + I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); > > + > > /* 5: Enable RPS */ > > I915_WRITE(GEN6_RP_CONTROL, > > GEN6_RP_MEDIA_HW_NORMAL_MODE | > > - GEN6_RP_MEDIA_IS_GFX | > > + GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ > > GEN6_RP_ENABLE | > > GEN6_RP_UP_BUSY_AVG | > > GEN6_RP_DOWN_IDLE_AVG); > > -- > > 1.7.9.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
