Adding Deepak for testing, this hopefully alleviates the bad side-effects of the gpu booster he's seeing. -Daniel On Thu, Jun 12, 2014 at 11:28 AM, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > Make the assumption that media workloads are not as latency sensitive > for __wait_seqno, and that upclocking the GPU does not affect the BLT > engine. Under that assumption, we only wait to forcibly upclock the GPU > when we are stalling for results from the render pipeline. > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 5951618a6b08..242b595a0403 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -1409,7 +1409,7 @@ static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, > > timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; > > - if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { > + if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { > gen6_rps_boost(dev_priv); > if (file_priv) > mod_delayed_work(dev_priv->wq, > -- > 2.0.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx