On Tue, Jun 10, 2014 at 10:09:52AM -0700, Rodrigo Vivi wrote: > These PCI IDs are reserved on BSpec and can be used at any time in the future. > So let's add this now in order to avoid issues that we already faced on previous > platforms, like finding out about new ids when user reported accelaration weren't > enabled. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > include/drm/i915_pciids.h | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 0572035..a70d456 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -237,13 +237,21 @@ > #define INTEL_BDW_GT3D_IDS(info) \ > _INTEL_BDW_D_IDS(3, info) > > +#define INTEL_BDW_RSVDM_IDS(info) \ > + _INTEL_BDW_M_IDS(4, info) > + > +#define INTEL_BDW_RSVDD_IDS(info) \ > + _INTEL_BDW_D_IDS(4, info) > + Assuming the IDs are ever used, the gt count should be right. 4 is invalid. Can you please use the correct GT value for the reserved IDs? I wouldn't bother creating a separate reserved structure since we already have the list. > #define INTEL_BDW_M_IDS(info) \ > INTEL_BDW_GT12M_IDS(info), \ > - INTEL_BDW_GT3M_IDS(info) > + INTEL_BDW_GT3M_IDS(info), \ > + INTEL_BDW_RSVDM_IDS(info) > > #define INTEL_BDW_D_IDS(info) \ > INTEL_BDW_GT12D_IDS(info), \ > - INTEL_BDW_GT3D_IDS(info) > + INTEL_BDW_GT3D_IDS(info), \ > + INTEL_BDW_RSVDD_IDS(info) > > #define INTEL_CHV_IDS(info) \ > INTEL_VGA_DEVICE(0x22b0, info), \ > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
