Hi Dave,
Bunch of stuff for 3.16 still:
- Mipi dsi panel support for byt. Finally! From Shobhit&others. I've
squeezed this in since it's a regression compared to vbios and we've
been ridiculed about it a bit too often ...
- connection_mutex deadlock fix in get_connector (only affects i915).
- Core patches from Matt's primary plane from Matt Roper, I've pushed the
i915 stuff to 3.17.
- vlv power well sequencing fixes from Jesse.
- Fix for cursor size changes from Chris.
- agpbusy fixes from Ville.
- A few smaller things.
>From here on Jani will take over shepherding 3.16.
Cheers, Daniel
The following changes since commit 5ea1f752ae04be403a3dc8ec876a60d7f5f6990a:
drm: add drm_fb_helper_restore_fbdev_mode_unlocked() (2014-06-05 10:02:40 +1000)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel danvet/drm-intel-fixes
for you to fetch changes up to 15d24aa5602fb87c7b1358cfabcfeb9b26db290f:
drm/i915: BDW: Adding missing cursor offsets. (2014-06-05 16:10:29 +0200)
----------------------------------------------------------------
Akash Goel (1):
drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
Ben Widawsky (1):
drm/i915/bdw: Only use 2g GGTT for 32b platforms
Chris Wilson (2):
drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object
drm/i915: Always apply cursor width changes
Daniel Vetter (8):
drm/i915: Add fifo underrun reporting state to debugfs
drm/i915: Fix up fifo underrun tracking, take N
drm/i915: Disable gpu reset on i965g/gm
drm/i915: Inline ilk/gen8_irq_reset
drm/i915: Improve irq handling after gpu resets
drm/i915: Extract gen8_gt_irq_reset
drm/i915: Nuke pipe A quirk on i830M
drm: Fix getconnector connection_mutex locking
Imre Deak (2):
drm/i915: dsi: fix pipe-off timeout due to port vs. pipe disable ordering
drm/i915: fix display power sw state reporting
Jani Nikula (1):
drm/i915: tell the user if both KMS and UMS are disabled
Jesse Barnes (7):
drm/i915/vlv: assert and de-assert sideband reset at boot and resume v3
drm/i915/vlv: drop power well enable in uncore_sanitize
drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well
drm/i915/vlv: re-order power wells so DPIO common comes after TX
drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well
drm/i915/vlv: add pll assertion when disabling DPIO common well
drm/i915: use VBT to determine whether to enumerate the VGA port
Matt Roper (2):
drm: Check CRTC compatibility in setplane
drm/plane-helper: Add drm_plane_helper_check_update() (v3)
Rodrigo Vivi (1):
drm/i915: BDW: Adding missing cursor offsets.
Shobhit Kumar (2):
drm/i915: Add support for Generic MIPI panel driver
drm/i915: Detect if MIPI panel based on VBT and initialize only if present
Ville Syrjälä (5):
drm/i915: Set AGPBUSY# bit in init_clock_gating
drm/i915: Flip the sense of AGPBUSY_DIS bit
drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS
drm/i915: Don't WARN about ring idle bit on gen2
drivers/gpu/drm/drm_crtc.c | 11 +-
drivers/gpu/drm/drm_plane_helper.c | 131 +++++--
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 19 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +
drivers/gpu/drm/i915/i915_irq.c | 83 ++--
drivers/gpu/drm/i915/i915_reg.h | 6 +-
drivers/gpu/drm/i915/intel_bios.c | 13 +
drivers/gpu/drm/i915/intel_bios.h | 4 +
drivers/gpu/drm/i915/intel_display.c | 145 ++++---
drivers/gpu/drm/i915/intel_drv.h | 6 +-
drivers/gpu/drm/i915/intel_dsi.c | 30 +-
drivers/gpu/drm/i915/intel_dsi.h | 2 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 589 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 95 ++++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 21 +-
include/drm/drm_plane_helper.h | 22 ++
21 files changed, 981 insertions(+), 218 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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