On Wed, 2014-05-28 at 15:27 +0530, sourab gupta wrote:
> On Mon, 2014-04-14 at 09:45 +0000, Gupta, Sourab wrote:
> > From: Akash Goel <akash.goel@xxxxxxxxx>
> >
> > This workaround is needed on VLV for the HW context feature.
> > It is used after adding the mi_set_context command in ring buffer
> > for Hw context switch. As per the spec
> > "The software must send a pipe_control with a CS stall and a post sync
> > operation and then a dummy DRAW after every MI_SET_CONTEXT and after any
> > PIPELINE_SELECT that is enabling 3D mode".
> > Tested only for vlv.
> >
> > v2: Modified the WA comment. (Ville)
> >
> > v3: Added the vlv identifier with the WA name
> >
> > v4: Check removed for scratch page initialization. (Chris/Daniel)
> >
> > v5: Refactored based on latest codebase. Also WA added for full Gen7.
> >
> > Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx>
> > Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_gem_context.c | 55 +++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++++++
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> > 4 files changed, 64 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f77b4c1..b6d2a67 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -545,6 +545,47 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
> > return ctx;
> > }
> >
> > +static inline void
> > +mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring)
> > +{
> > + u32 scratch_addr;
> > + u32 flags = 0;
> > +
> > + /* Actual scratch location is at 128 bytes offset */
> > + scratch_addr = intel_get_pipe_control_scratch_addr(ring) + 128;
> > +
> > + /*
> > + * WaSendDummy3dPrimitveAfterSetContext:ivb,vlv
> > + * Software must send a pipe_control with a CS stall
> > + * and a post sync operation and then a dummy DRAW after
> > + * every MI_SET_CONTEXT and after any PIPELINE_SELECT that
> > + * is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command
> > + * with Indirect Parameter Enable set to 0, UAV Coherency
> > + * Required set to 0, Predicate Enable set to 0,
> > + * End Offset Enable set to 0, and Vertex Count Per Instance
> > + * set to 0, All other parameters are a don't care.
> > + */
> > +
> > + /*
> > + * Add a pipe control with CS Stall and postsync op
> > + * before dummy 3D_PRIMITIVE
> > + */
> > + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
> > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
> > + intel_ring_emit(ring, flags);
> > + intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
> > + intel_ring_emit(ring, 0);
> > +
> > + /* Add a dummy 3D_PRIMITVE */
> > + intel_ring_emit(ring, GFX_OP_3DPRIMITIVE);
> > + intel_ring_emit(ring, 4); /* PrimTopoType*/
> > + intel_ring_emit(ring, 0); /* VertexCountPerInstance */
> > + intel_ring_emit(ring, 0); /* StartVertexLocation */
> > + intel_ring_emit(ring, 0); /* InstanceCount */
> > + intel_ring_emit(ring, 0); /* StartInstanceLocation */
> > + intel_ring_emit(ring, 0); /* BaseVertexLocation */
> > +}
> > +
> > static inline int
> > mi_set_context(struct intel_ring_buffer *ring,
> > struct i915_hw_context *new_context,
> > @@ -563,7 +604,10 @@ mi_set_context(struct intel_ring_buffer *ring,
> > return ret;
> > }
> >
> > - ret = intel_ring_begin(ring, 6);
> > + if (INTEL_INFO(ring->dev)->gen == 7)
> > + ret = intel_ring_begin(ring, 6+4+8);
> > + else
> > + ret = intel_ring_begin(ring, 6);
> > if (ret)
> > return ret;
> >
> > @@ -586,8 +630,15 @@ mi_set_context(struct intel_ring_buffer *ring,
> > */
> > intel_ring_emit(ring, MI_NOOP);
> >
> > + /* WaSendDummy3dPrimitveAfterSetContext:ivb,vlv */
> > if (INTEL_INFO(ring->dev)->gen >= 7)
> > - intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
> > + if (INTEL_INFO(ring->dev)->gen == 7) {
> > + mi_set_context_dummy3d_prim_wa(ring);
> > + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
> > + intel_ring_emit(ring, MI_NOOP);
> > + } else
> > + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
> > +
> > else
> > intel_ring_emit(ring, MI_NOOP);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8f84555..1128527 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -355,6 +355,7 @@
> > #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
> > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> > +#define GFX_OP_3DPRIMITIVE ((0x3<<29)|(0x3<<27)|(0x3<<24)|(7-2))
> >
> > /*
> > * Commands used only by the command parser
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index eb3dd26..834411b 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -585,6 +585,15 @@ err:
> > return ret;
> > }
> >
> > +u32
> > +intel_get_pipe_control_scratch_addr(struct intel_ring_buffer *ring)
> > +{
> > + if (ring->scratch.obj == NULL)
> > + return 0;
> > +
> > + return ring->scratch.gtt_offset;
> > +}
> > +
> > static int init_render_ring(struct intel_ring_buffer *ring)
> > {
> > struct drm_device *dev = ring->dev;
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index 413cdc7..ffaed8b 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -291,6 +291,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev);
> >
> > u64 intel_ring_get_active_head(struct intel_ring_buffer *ring);
> > void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
> > +u32 intel_get_pipe_control_scratch_addr(struct intel_ring_buffer *ring);
> >
> > static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
> > {
>
> Hi,
>
> Can you please review this WA patch.
>
> Thanks,
> Sourab
>
Hi,
Can you please provide your comments on above WA patch.
Thanks,
Sourab
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