On Tue, 03 Jun 2014, clinton.a.taylor@xxxxxxxxx wrote: > From: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx> > > The panel power sequencer on vlv doesn't appear to accept changes to its > T12 power down duration during warm reboots. This change forces a delay > for warm reboots to the T12 panel timing as defined in the VBT table for > the connected panel. > > Ver2: removed redundant pr_crit(), commented magic value for pp_div_reg > > Ver3: moved SYS_RESTART check earlier, new name for pp_div. > > Ver4: Minor issue changes > Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > Signed-off-by: Clint Taylor <clinton.a.taylor@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_dp.c | 42 ++++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 2 files changed, 44 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 5ca68aa9..cede9bc 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -28,6 +28,8 @@ > #include <linux/i2c.h> > #include <linux/slab.h> > #include <linux/export.h> > +#include <linux/notifier.h> > +#include <linux/reboot.h> > #include <drm/drmP.h> > #include <drm/drm_crtc.h> > #include <drm/drm_crtc_helper.h> > @@ -302,6 +304,38 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp) > return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); > } > > +/* Reboot notifier handler to shutdown panel power to guarantee T12 timing */ > +static int edp_notify_handler(struct notifier_block *this, unsigned long code, > + void *unused) > +{ > + struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), > + edp_notifier); > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct drm_device *dev = intel_dig_port->base.base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + u32 pp_div; > + u32 pp_ctrl_reg, pp_div_reg; > + enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); > + > + if (!is_edp(intel_dp) || code != SYS_RESTART ) > + return 0; > + > + if (IS_VALLEYVIEW(dev)) { > + pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); > + pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); > + pp_div = I915_READ(VLV_PIPE_PP_DIVISOR(pipe)); > + pp_div &= PP_REFERENCE_DIVIDER_MASK; > + > + /* 0x1F write to PP_DIV_REG sets max cycle delay */ > + I915_WRITE(pp_div_reg, pp_div | 0x1F); > + I915_WRITE(pp_ctrl_reg, > + PANEL_UNLOCK_REGS | PANEL_POWER_OFF); > + msleep(intel_dp->panel_power_cycle_delay); > + } > + > + return 0; > +} > + > static bool edp_have_panel_power(struct intel_dp *intel_dp) > { > struct drm_device *dev = intel_dp_to_dev(intel_dp); > @@ -3344,6 +3378,10 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) > mutex_lock(&dev->mode_config.mutex); > edp_panel_vdd_off_sync(intel_dp); > mutex_unlock(&dev->mode_config.mutex); > + if (intel_dp->edp_notifier.notifier_call) { > + unregister_reboot_notifier(&intel_dp->edp_notifier); > + intel_dp->edp_notifier.notifier_call = NULL; > + } > } > kfree(intel_dig_port); > } > @@ -3782,6 +3820,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > if (is_edp(intel_dp)) { > intel_dp_init_panel_power_timestamps(intel_dp); > intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > + if (IS_VALLEYVIEW(dev)) { > + intel_dp->edp_notifier.notifier_call = edp_notify_handler; > + register_reboot_notifier(&intel_dp->edp_notifier); > + } > } > > intel_dp_aux_init(intel_dp, intel_connector); > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 328b1a7..6d0d96e 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -510,6 +510,8 @@ struct intel_dp { > unsigned long last_power_on; > unsigned long last_backlight_off; > bool psr_setup_done; > + struct notifier_block edp_notifier; > + > bool use_tps3; > struct intel_connector *attached_connector; > > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx