On Tue, May 27, 2014 at 01:45:59PM +0300, Mika Kuoppala wrote:
> deepak.s@xxxxxxxxxxxxxxx writes:
>
> > From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> >
> > v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
> >
> > v3: Mass rename of the dev_priv->rps variables in upstream.
> >
> > v4: Rebase against latest code. (Deepak)
> >
> > v5: Rebase against latest nightly code. (Deepak)
> >
> > v6: Rename the variables to match the spec (Mika)
> >
> > v7: change min/max freq variable naming to match spec (Mika)
> >
> > Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> > ---
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Ok, I've merged all remaining patches except for patch 6. This one here
angered checkpatch a bit, please check your patches before submission if
you don't have a text editor which just gets all the little alignment
recommendations right.
Thanks, Daniel
>
> > drivers/gpu/drm/i915/i915_reg.h | 11 +++++
> > drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++++++++++++++++-
> > 2 files changed, 102 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c1f36a5..8a935cf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -529,6 +529,16 @@ enum punit_power_well {
> > #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> > #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
> >
> > +#define PUNIT_GPU_STATUS_REG 0xdb
> > +#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> > +#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> > +#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
> > +#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
> > +
> > +#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
> > +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
> > +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
> > +
> > #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> > #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> > #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> > @@ -933,6 +943,7 @@ enum punit_power_well {
> > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
> > #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
> >
> > +
> > /* control register for cpu gtt access */
> > #define TILECTL 0x101000
> > #define TILECTL_SWZCTL (1 << 0)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 1816c52..0f36405 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > }
> >
> > +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val, rp0;
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> > + rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> > +
> > + return rp0;
> > +}
> > +
> > +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val, rpe;
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
> > + rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
> > +
> > + return rpe;
> > +}
> > +
> > +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val, rpn;
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> > + rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
> > + return rpn;
> > +}
> > +
> > int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> > {
> > u32 val, rp0;
> > @@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
> >
> > static void cherryview_init_gt_powersave(struct drm_device *dev)
> > {
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > cherryview_setup_pctx(dev);
> > +
> > + mutex_lock(&dev_priv->rps.hw_lock);
> > +
> > + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> > + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> > + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> > + dev_priv->rps.max_freq);
> > +
> > + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> > + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > + dev_priv->rps.efficient_freq);
> > +
> > + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> > + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> > + dev_priv->rps.min_freq);
> > +
> > + /* Preserve min/max settings in case of re-init */
> > + if (dev_priv->rps.max_freq_softlimit == 0)
> > + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
> > +
> > + if (dev_priv->rps.min_freq_softlimit == 0)
> > + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
> > +
> > + mutex_unlock(&dev_priv->rps.hw_lock);
> > }
> >
> > static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
> > @@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_engine_cs *ring;
> > - u32 gtfifodbg, rc6_mode = 0, pcbr;
> > + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
> > int i;
> >
> > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > @@ -3949,6 +4007,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >
> > I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> >
> > + /* 4 Program defaults and thresholds for RPS*/
> > + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> > + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> > + I915_WRITE(GEN6_RP_UP_EI, 66000);
> > + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
> > +
> > + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> > +
> > + /* 5: Enable RPS */
> > + I915_WRITE(GEN6_RP_CONTROL,
> > + GEN6_RP_MEDIA_HW_NORMAL_MODE |
> > + GEN6_RP_MEDIA_IS_GFX |
> > + GEN6_RP_ENABLE |
> > + GEN6_RP_UP_BUSY_AVG |
> > + GEN6_RP_DOWN_IDLE_AVG);
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > +
> > + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> > + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> > +
> > + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> > + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> > + dev_priv->rps.cur_freq);
> > +
> > + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > + dev_priv->rps.efficient_freq);
> > +
> > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> > +
> > gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> > }
> >
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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