On Thu, May 22, 2014 at 05:56:31PM +0200, Daniel Vetter wrote: > On platforms with shared interrupt enable bits (which are shared even > with the pipe CRC logic) there's some tricky corner cases. Add > information to make debugging those easier. > > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> For patches 1,3,4: Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 16bbdc7243df..4a79d3fe35be 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2356,6 +2356,10 @@ static int i915_display_info(struct seq_file *m, void *unused) > x, y, crtc->cursor_addr, > yesno(active)); > } > + > + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", > + yesno(!crtc->cpu_fifo_underrun_disabled), > + yesno(!crtc->pch_fifo_underrun_disabled)); > } > > seq_printf(m, "\n"); > -- > 1.8.4.rc3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx