And to answer more specifically... On Wed, 21 May 2014 20:54:03 +0300 Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > + __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, > > + false); > > + __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, > > + true); > > Hmm. I wonder how the power well hack in intel_uncore_sanitize() ties in > with this. We should definitely rip that out regardless. Yeah we can rip that out. That's just an ungate, and it assumes the BIOS has already done the reset toggle for us. > Another thing I'm wodering is did the BIOS/hw really power on the > common lane, or did we do that outselves? If the latter, then I wonder > if we simply do that too early. Or more precisely do we need to make > sure the cri clock and/or refclock are enabled before we power on the > common lane? Depends on the platform. It looks like the right thing happens at boot time on most machines (i.e. the BIOS does a full toggle which causes a reset), but on suspend/resume it's up to us. And of course on machines without video init at boot time, we need to do it ourselves as well. I don't think the cri or refclk is required at this point, at least not if the docs we have are correct (the PHY reset is supposed to be the very first thing). > And third is that do we need to enable the TX wells before the CMN > well? Currently we do the opposite which could also explain why this > CMN well toggle fixes things. I don't think that matters, but we should ask the PHY guys. The lack of symmetry between the gate and ungate bothers me too. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
