On 16 May 2014 17:40, <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> FIFO underruns don't generate interrupts on gmch platforms, so
> if we want to know whether a modeset triggered FIFO underruns we
> need to explicitly check for them.
>
> As a modeset on one pipe could cause underruns on other pipes,
> check for underruns on all pipes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Thomas Wood <thomas.wood@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 6 ++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8bb564b..fdce260 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -266,6 +266,34 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
> return true;
> }
>
> +void i9xx_check_fifo_underruns(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *crtc;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dev_priv->irq_lock, flags);
> +
> + for_each_intel_crtc(dev, crtc) {
> + u32 reg = PIPESTAT(crtc->pipe);
> + u32 pipestat;
> +
> + if (crtc->cpu_fifo_underrun_disabled)
> + continue;
> +
> + pipestat = I915_READ(reg) & 0xffff0000;
> + if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
> + continue;
> +
> + I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
> + POSTING_READ(reg);
> +
> + DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
> + }
> +
> + spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> +}
> +
> static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
> enum pipe pipe, bool enable)
> {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0f8f9bc..1b5164c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4545,6 +4545,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_enable_planes(crtc);
>
> drm_vblank_on(dev, pipe);
> +
> + /* Underruns don't raise interrupts, so check manually. */
> + i9xx_check_fifo_underruns(dev);
> }
>
> static void i9xx_crtc_enable(struct drm_crtc *crtc)
> @@ -4581,6 +4584,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_enable_planes(crtc);
>
> drm_vblank_on(dev, pipe);
> +
> + /* Underruns don't raise interrupts, so check manually. */
> + i9xx_check_fifo_underruns(dev);
> }
>
> static void i9xx_pfit_disable(struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 32a74e1..db0a74d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -671,6 +671,7 @@ void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
> void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
> int intel_get_crtc_scanline(struct intel_crtc *crtc);
> +void i9xx_check_fifo_underruns(struct drm_device *dev);
>
>
> /* intel_crt.c */
> --
> 1.8.5.5
>
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