On Wed, May 21, 2014 at 04:40:04PM +0530, Vandana Kannan wrote:
> Adding relevant read out comparison code, in check_crtc_state, for the new
> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
> values for a DP downclock mode (if available). Suggested by Daniel.
>
> v2: Changed patch title.
> Daniel's review comments incorporated.
> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
> only when high RR is not in use (This is because alternate m_n register
> programming will be done only when low RR is being used).
>
> v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake.
> Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures
> based on DRRS state for gen 8 and above.
> Save and restore M2 N2 registers for gen 7 and below
>
> v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is
> only one set of M_N registers
>
> Signed-off-by: Vandana Kannan <vandana.kannan@xxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
Some comments below.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 ++++
> drivers/gpu/drm/i915/i915_ums.c | 26 +++++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_dp.c | 2 +
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 6 files changed, 117 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b82f157..a06551a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -815,6 +815,14 @@ struct i915_suspend_saved_registers {
> u32 savePIPEB_DATA_N1;
> u32 savePIPEB_LINK_M1;
> u32 savePIPEB_LINK_N1;
> + u32 savePIPEA_DATA_M2;
> + u32 savePIPEA_DATA_N2;
> + u32 savePIPEA_LINK_M2;
> + u32 savePIPEA_LINK_N2;
> + u32 savePIPEB_DATA_M2;
> + u32 savePIPEB_DATA_N2;
> + u32 savePIPEB_LINK_M2;
> + u32 savePIPEB_LINK_N2;
> u32 saveMCHBAR_RENDER_STANDBY;
> u32 savePCH_PORT_HOTPLUG;
> };
> diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
> index 480da59..82fc08f 100644
> --- a/drivers/gpu/drm/i915/i915_ums.c
> +++ b/drivers/gpu/drm/i915/i915_ums.c
> @@ -141,6 +141,21 @@ void i915_save_display_reg(struct drm_device *dev)
> dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
> dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
>
> + /* Saving M2_N2 registers only for Gen7 because DRRS will be
> + * used only from Gen7 and for Gen8 & above there is no
> + * M2_N2 register.
> + */
> + if (INTEL_INFO(dev)->gen == 7) {
> + dev_priv->regfile.savePIPEA_DATA_M2 =
> + I915_READ(_PIPEA_DATA_M2);
> + dev_priv->regfile.savePIPEA_DATA_N2 =
> + I915_READ(_PIPEA_DATA_N2);
> + dev_priv->regfile.savePIPEA_LINK_M2 =
> + I915_READ(_PIPEA_LINK_M2);
> + dev_priv->regfile.savePIPEA_LINK_N2 =
> + I915_READ(_PIPEA_LINK_N2);
> + }
> +
> dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
> dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
>
> @@ -407,6 +422,17 @@ void i915_restore_display_reg(struct drm_device *dev)
> I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
> I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
>
> + if (INTEL_INFO(dev)->gen == 7) {
> + I915_WRITE(_PIPEA_DATA_M2,
> + dev_priv->regfile.savePIPEA_DATA_M2);
> + I915_WRITE(_PIPEA_DATA_N2,
> + dev_priv->regfile.savePIPEA_DATA_N2);
> + I915_WRITE(_PIPEA_LINK_M2,
> + dev_priv->regfile.savePIPEA_LINK_M2);
> + I915_WRITE(_PIPEA_LINK_N2,
> + dev_priv->regfile.savePIPEA_LINK_N2);
> + }
These three hunks shouldn't be required since we restore the full mode in
the crtc_enable callback. We should _never_ add new register restore code
to this since maintaining such code is a major pain.
> +
> I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
> I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0ad4e96..6784f0b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> case TRANS_DDI_MODE_SELECT_DP_MST:
> pipe_config->has_dp_encoder = true;
> intel_dp_get_m_n(intel_crtc, pipe_config);
> + intel_dp_get_m2_n2(intel_crtc, pipe_config);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cf3ad87..09fc286 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6980,6 +6980,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> &pipe_config->dp_m_n);
> }
>
> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
Imo simpler if you just move the code into intel_dp_get_m_n instead.
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum transcoder transcoder = pipe_config->cpu_transcoder;
> +
> + if (INTEL_INFO(dev)->gen >= 8) {
> + intel_cpu_transcoder_get_m_n(crtc, transcoder,
> + &pipe_config->dp_m2_n2);
We shouldn't fake dp M2/N2 on bdw like this - they just don't exist.
> + } else if (INTEL_INFO(dev)->gen > 6) {
These registers exists since ilk, so the check here should be gen >= 5.
Also please check the situation on vlv, I don't have the latest docs handy
for those.
> + pipe_config->dp_m2_n2.link_m =
> + I915_READ(PIPE_LINK_M2(transcoder));
> + pipe_config->dp_m2_n2.link_n =
> + I915_READ(PIPE_LINK_N2(transcoder));
> + pipe_config->dp_m2_n2.gmch_m =
> + I915_READ(PIPE_DATA_M2(transcoder))
> + & ~TU_SIZE_MASK;
> + pipe_config->dp_m2_n2.gmch_n =
> + I915_READ(PIPE_DATA_N2(transcoder));
> + pipe_config->dp_m2_n2.tu =
> + ((I915_READ(PIPE_DATA_M2(transcoder))
> + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> + }
> +
> +}
> +
> +
> static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config)
> {
> @@ -9485,6 +9513,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
> pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
> pipe_config->dp_m_n.tu);
> +
> + DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
> + pipe_config->has_dp_encoder,
> + pipe_config->dp_m2_n2.gmch_m,
> + pipe_config->dp_m2_n2.gmch_n,
> + pipe_config->dp_m2_n2.link_m,
> + pipe_config->dp_m2_n2.link_n,
> + pipe_config->dp_m2_n2.tu);
> +
> DRM_DEBUG_KMS("requested mode:\n");
> drm_mode_debug_printmodeline(&pipe_config->requested_mode);
> DRM_DEBUG_KMS("adjusted mode:\n");
> @@ -9867,6 +9904,26 @@ intel_pipe_config_compare(struct drm_device *dev,
> return false; \
> }
>
> +/* This is required for BDW+ where there is only one set of registers for
> + * switching between high and low RR.
> + * This macro can be used whenever a comparison has to be made between one
> + * hw state and multiple sw state variables.
> + */
> +#define PIPE_CONF_CHECK_I_I(name1, name2) \
> + if (current_config->name1 != pipe_config->name1) { \
> + DRM_ERROR("mismatch in " #name1 " " \
> + "(expected %i, found %i)\n", \
> + current_config->name1, \
> + pipe_config->name1); \
The DRM_ERROR here is wrong, you should only warn if neither of them
match. Also I with the bdw readout for m2/n2 removed this won't work. And
I think we need a better name for this macro. What about
# define PIPE_CONF_CHECK_I_ALT(name, alternate_name) \
if ((current_config->name != pipe_config->name) && \
(current_config->name != pipe_config->alternate_name) { \
... error stuff ... \
}
> + if (current_config->name2 != pipe_config->name2) { \
> + DRM_ERROR("mismatch in " #name2 " " \
> + "(expected %i, found %i)\n", \
> + current_config->name2, \
> + pipe_config->name2); \
> + return false; \
> + } \
> + }
> +
> #define PIPE_CONF_CHECK_FLAGS(name, mask) \
> if ((current_config->name ^ pipe_config->name) & (mask)) { \
> DRM_ERROR("mismatch in " #name "(" #mask ") " \
> @@ -9899,11 +9956,26 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_I(fdi_m_n.tu);
>
> PIPE_CONF_CHECK_I(has_dp_encoder);
> - PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
> - PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
> - PIPE_CONF_CHECK_I(dp_m_n.link_m);
> - PIPE_CONF_CHECK_I(dp_m_n.link_n);
> - PIPE_CONF_CHECK_I(dp_m_n.tu);
> +
> + if (INTEL_INFO(dev)->gen < 8) {
> + PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
> + PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
> + PIPE_CONF_CHECK_I(dp_m_n.link_m);
> + PIPE_CONF_CHECK_I(dp_m_n.link_n);
> + PIPE_CONF_CHECK_I(dp_m_n.tu);
> +
> + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
> + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
> + PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
> + PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
> + PIPE_CONF_CHECK_I(dp_m2_n2.tu);
> + } else {
> + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
> + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
> + PIPE_CONF_CHECK_I_I(dp_m_n.link_m, dp_m2_n2.link_m);
> + PIPE_CONF_CHECK_I_I(dp_m_n.link_n, dp_m2_n2.link_n);
> + PIPE_CONF_CHECK_I_I(dp_m_n.tu, dp_m2_n2.tu);
> + }
>
> PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
> PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
> @@ -9980,6 +10052,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> +#undef PIPE_CONF_CHECK_I_I
> #undef PIPE_CONF_CHECK_FLAGS
> #undef PIPE_CONF_CHECK_CLOCK_FUZZY
> #undef PIPE_CONF_QUIRK
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bcab4ea..c55f827 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1555,6 +1555,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>
> intel_dp_get_m_n(crtc, pipe_config);
>
> + intel_dp_get_m2_n2(crtc, pipe_config);
> +
> if (port == PORT_A) {
> if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
> pipe_config->port_clock = 162000;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5233a3d..2b4cd30 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -778,6 +778,8 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config);
> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> void
> ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
> --
> 1.9.3
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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