On Mon, 19 May 2014 16:16:37 -0700 Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> wrote: > This is a bit like the CMN reset de-assert we do in DPIO_CTL, except > that it resets the whole common lane section of the PHY. This is > required on machines where the BIOS doesn't do this for us on boot or > resume to properly re-calibrate and get the PHY ready to transmit data. > > Without this patch, such machines won't resume correctly much of the time, > with the symptom being a 'port ready' timeout and/or a link training > failure. > > v2: extract simpler set_power_well function for use in reset_dpio (Imre) > move to reset_dpio (Daniel & Ville) Summarizing the IRC discussion because we're terrible about doing that. Imre was concerned that this new unconditional reset would prevent fastboot from working, and I think he's right. I added a check for the DPIO reset de-assertion for that case, and it seems to do the right thing on my BYT here (skipping the reset on boot since the BIOS already did it, and doing it on resume since the BIOS hadn't). Patch is in the next mail. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
