On Tue, May 20, 2014 at 4:11 PM, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > On Tue, May 20, 2014 at 03:50:02PM +0200, Daniel Vetter wrote: >> On Wed, Apr 09, 2014 at 07:56:50PM +0300, Ville Syrjälä wrote: >> > On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote: >> > > On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: >> > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> > > > >> > > > All PCS groups access reads return 0xffffffff, so we can't use group >> > > > access for RMW cycles. Instead target each spline separately. >> > > >> > > I have no idea what PCS means here and spline ... Can you please expand >> > > for those who haven't yet lost their souls in chv docs? Just so we have a >> > > commonly-understood jargon for talking about this stuff. >> > >> > I guess we should have that somewhere as a comment. The same terminology >> > applies to VLV as well. >> >> Haven't seen the promised patch yet. > > "[PATCH] drm/i915: Add a brief description of the VLV display PHY internals" & co. Indeed, but fell through the review cracks :( -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
