On Mon, Apr 28, 2014 at 07:19:50PM -0300, Paulo Zanoni wrote: > 2014-04-28 5:23 GMT-03:00 Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>: > > On Fri, Apr 25, 2014 at 05:55:38PM -0300, Paulo Zanoni wrote: > >> 2014-04-09 7:28 GMT-03:00 <ville.syrjala@xxxxxxxxxxxxxxx>: > >> > From: Rafael Barbalho <rafael.barbalho@xxxxxxxxx> > >> > > >> > Cherryview also needs this WA. > >> > >> At least on the chv_rebase tree, this WA is implemented for BDW but it > >> is not documented as pre-prod only, and its name is not there. We > >> should probably add a comment documenting the name and the fact that > >> it is also pre-prod on BDW. > > > > IIRC BDW will need it even on production steppings. > > Hmmm the register documentation says one thing while the WA lists say > others... I'll let you discover which one is correct :) > > > > > I think I have a patch somewhere that add the w/a note for BDW, but I guess > > I didn't post it yet. > > > >> > >> > >> > > >> > Signed-off-by: Rafael Barbalho <rafael.barbalho@xxxxxxxxx> > >> > [vsyrjala: Looks like it's for pre-prodution hw only] > >> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > >> > --- > >> > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > >> > 1 file changed, 4 insertions(+) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >> > index 468fe37..60f876c 100644 > >> > --- a/drivers/gpu/drm/i915/intel_pm.c > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c > >> > @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev) > >> > /* WaDisableSDEUnitClockGating:chv */ > >> > I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > >> > GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > >> > + > >> > + /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ > >> > + I915_WRITE(HALF_SLICE_CHICKEN3, > >> > + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); > >> > >> I could not find information anywhere if this is the correct > >> implementation. Can you please provide me pointers to the doc you > >> used? The links on Collab seem broken. > > > > Just w/a database + bspec are enough for this one. > > Found it :) > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> Merged up to this patch (except for the rps patches). -Daniel > > > > >> > >> Thanks, > >> Paulo > >> > >> > } > >> > > >> > static void g4x_init_clock_gating(struct drm_device *dev) > >> > -- > >> > 1.8.3.2 > >> > > >> > _______________________________________________ > >> > Intel-gfx mailing list > >> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> > >> > >> > >> -- > >> Paulo Zanoni > > > > -- > > Ville Syrjälä > > Intel OTC > > > > -- > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
