On Thu, Apr 24, 2014 at 11:55:41PM +0200, Daniel Vetter wrote:
> To be able to do this we need to separately keep track of how many
> crtcs need a given WRPLL and how many actually actively use it. The
> common shared dpll framework already has all this, including massive
> state readout and cross checking. Which allows us to do this switch in
> a fairly small patch.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 12 +-----------
> drivers/gpu/drm/i915/intel_display.c | 16 +++++++---------
> drivers/gpu/drm/i915/intel_drv.h | 2 --
> 3 files changed, 8 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7386a1212e71..97f9cd6dbee1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -255,16 +255,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
> return ret;
> }
>
> -void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
> -{
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -
> - if (intel_crtc_to_shared_dpll(intel_crtc))
> - intel_disable_shared_dpll(intel_crtc);
> -
> - intel_put_shared_dpll(intel_crtc);
> -}
> -
> #define LC_FREQ 2700
> #define LC_FREQ_2K (LC_FREQ * 2000)
>
> @@ -585,7 +575,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
> int type = intel_encoder->type;
> int clock = intel_crtc->config.port_clock;
>
> - intel_ddi_put_crtc_pll(crtc);
> + intel_put_shared_dpll(intel_crtc);
>
> if (type == INTEL_OUTPUT_HDMI) {
> struct intel_shared_dpll *pll;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2fd77eba57f3..e0bd0f94e43e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3673,6 +3673,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->active)
> return;
>
> + if (intel_crtc_to_shared_dpll(intel_crtc))
> + intel_enable_shared_dpll(intel_crtc);
> +
> if (intel_crtc->config.has_dp_encoder)
> intel_dp_set_m_n(intel_crtc);
>
> @@ -3846,6 +3849,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> intel_update_fbc(dev);
> intel_edp_psr_update(dev);
> mutex_unlock(&dev->struct_mutex);
> +
> + if (intel_crtc_to_shared_dpll(intel_crtc))
> + intel_disable_shared_dpll(intel_crtc);
> }
>
> static void ironlake_crtc_off(struct drm_crtc *crtc)
> @@ -3854,11 +3860,6 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
> intel_put_shared_dpll(intel_crtc);
> }
>
> -static void haswell_crtc_off(struct drm_crtc *crtc)
> -{
> - intel_ddi_put_crtc_pll(crtc);
> -}
> -
> static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
> {
> if (!enable && intel_crtc->overlay) {
> @@ -7002,9 +7003,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> if (!intel_ddi_pll_select(intel_crtc))
> return -EINVAL;
>
> - if (intel_crtc_to_shared_dpll(intel_crtc))
> - intel_enable_shared_dpll(intel_crtc);
> -
> intel_crtc->lowfreq_avail = false;
>
> return 0;
> @@ -10904,7 +10902,7 @@ static void intel_init_display(struct drm_device *dev)
> dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
> dev_priv->display.crtc_enable = haswell_crtc_enable;
> dev_priv->display.crtc_disable = haswell_crtc_disable;
> - dev_priv->display.off = haswell_crtc_off;
> + dev_priv->display.off = ironlake_crtc_off;
> dev_priv->display.update_primary_plane =
> ironlake_update_primary_plane;
> } else if (HAS_PCH_SPLIT(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index acd32e8e5e13..81a7813fc78b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -683,7 +683,6 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
> void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
> bool intel_ddi_pll_select(struct intel_crtc *crtc);
> -void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
> void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
> void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
> void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
> @@ -746,7 +745,6 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -void intel_disable_shared_dpll(struct intel_crtc *crtc);
> struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
> void intel_put_shared_dpll(struct intel_crtc *crtc);
>
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
