On Tue, May 20, 2014 at 11:56:28AM +0100, Damien Lespiau wrote: > On Thu, Apr 24, 2014 at 11:55:34PM +0200, Daniel Vetter wrote: > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -272,6 +272,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) > > I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); > > POSTING_READ(WRPLL_CTL1); > > } > > + intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE; > > break; > > case PORT_CLK_SEL_WRPLL2: > > plls->wrpll2_refcount--; > > @@ -282,13 +283,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) > > I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); > > POSTING_READ(WRPLL_CTL2); > > } > > + intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE; > > break; > > } > > > > WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); > > WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); > > - > > - intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE; > > } > > Who sets config.ddi_pll_sel to NONE for VGA and DP now? We don't care about that any more. The spll handling was completely moved into intel_crt.c with the intermediate patches, and intel DP directly keys off the right clock from config->port_clock. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
