On Thu, Apr 24, 2014 at 11:55:13PM +0200, Daniel Vetter wrote:
> This is the last piece of code which write state to the hardware in
> the ironalake ->crtc_mode_set callback.
>
> I think we could merge this with the pll->enable hook, but otoh the
> ordering requirements with the ldvs port are really tricky. Doing the
> FP0/1 writes up-front before we even prepare the lvds port (in the
> pre_pll_enable hook) like on i9xx seems safest.
>
> With this ilk+ platforms are now ready for runtime PM with DPMS. Since
> hsw/bdw also support runtime pm besides snb we need to first make the
> haswell code save before we can touch the core code.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++++++-------
> 1 file changed, 19 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index aef869dcc054..96bab640399f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1551,6 +1551,22 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> port_name(dport->port), I915_READ(DPLL(0)));
> }
>
> +static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> +
> + WARN_ON(!pll->refcount);
> + if (pll->active == 0) {
> + DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> + WARN_ON(pll->on);
> + assert_shared_dpll_disabled(dev_priv, pll);
> +
> + pll->mode_set(dev_priv, pll);
> + }
> +}
> +
> /**
> * ironlake_enable_shared_dpll - enable PCH PLL
> * @dev_priv: i915 private structure
> @@ -3462,13 +3478,6 @@ found:
> DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
> pipe_name(crtc->pipe));
>
> - if (pll->active == 0) {
> - DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> - WARN_ON(pll->on);
> - assert_shared_dpll_disabled(dev_priv, pll);
> -
> - pll->mode_set(dev_priv, pll);
> - }
> pll->refcount++;
>
> return pll;
> @@ -3699,6 +3708,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->active)
> return;
>
> + if (intel_crtc->config.has_pch_encoder)
> + intel_prepare_shared_dpll(intel_crtc);
> +
> if (intel_crtc->config.has_dp_encoder)
> intel_dp_set_m_n(intel_crtc);
>
> --
> 1.8.1.4
>
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