Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
---
lib/intel_io.h | 2 ++
lib/intel_iosf.c | 14 ++++++++++++++
tools/quick_dump/chipset.i | 2 ++
tools/quick_dump/quick_dump.py | 2 ++
tools/quick_dump/reg_access.py | 6 ++++++
tools/quick_dump/valleyview | 1 +
tools/quick_dump/vlv_flisdsi.txt | 39 +++++++++++++++++++++++++++++++++++++++
7 files changed, 66 insertions(+)
create mode 100644 tools/quick_dump/vlv_flisdsi.txt
diff --git a/lib/intel_io.h b/lib/intel_io.h
index d56d061..78a6f4d 100644
--- a/lib/intel_io.h
+++ b/lib/intel_io.h
@@ -48,6 +48,8 @@ void OUTREG(uint32_t reg, uint32_t val);
/* sideband access functions from intel_iosf.c */
uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
+uint32_t intel_flisdsi_reg_read(uint32_t reg);
+void intel_flisdsi_reg_write(uint32_t reg, uint32_t val);
int intel_punit_read(uint8_t addr, uint32_t *val);
int intel_punit_write(uint8_t addr, uint32_t val);
diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
index 26d6d01..ffa2fca 100644
--- a/lib/intel_iosf.c
+++ b/lib/intel_iosf.c
@@ -153,3 +153,17 @@ void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
}
+
+uint32_t intel_flisdsi_reg_read(uint32_t reg)
+{
+ uint32_t val = 0;
+
+ vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
+
+ return val;
+}
+
+void intel_flisdsi_reg_write(uint32_t reg, uint32_t val)
+{
+ vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
+}
diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i
index ae176e8..6dd92cc 100644
--- a/tools/quick_dump/chipset.i
+++ b/tools/quick_dump/chipset.i
@@ -18,6 +18,7 @@ extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
+extern uint32_t intel_flisdsi_reg_read(uint32_t reg);
%}
extern int is_sandybridge(unsigned short pciid);
@@ -33,3 +34,4 @@ extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
+extern uint32_t intel_flisdsi_reg_read(uint32_t reg);
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index bace8c7..523f675 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -38,6 +38,8 @@ def parse_file(file):
register = ast.literal_eval(line)
if register[2] == 'DPIO':
val = reg.dpio_read(register[1], 0)
+ if register[2] == 'FLISDSI':
+ val = reg.flisdsi_read(register[1])
else:
val = reg.read(register[1])
intreg = int(register[1], 16)
diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py
index 85f9b57..84fea7c 100755
--- a/tools/quick_dump/reg_access.py
+++ b/tools/quick_dump/reg_access.py
@@ -35,6 +35,12 @@ def dpio_read(reg, phy):
val = chipset.intel_dpio_reg_read(reg, phy)
return val
+def flisdsi_read(reg):
+ reg = int(reg, 16)
+
+ val = chipset.intel_flisdsi_reg_read(reg)
+ return val
+
def init():
pci_dev = chipset.intel_get_pci_device()
diff --git a/tools/quick_dump/valleyview b/tools/quick_dump/valleyview
index 6b6e16c..6c3441e 100644
--- a/tools/quick_dump/valleyview
+++ b/tools/quick_dump/valleyview
@@ -6,3 +6,4 @@ base_power.txt
base_rings.txt
gen7_other.txt
vlv_dpio.txt
+vlv_flisdsi.txt
diff --git a/tools/quick_dump/vlv_flisdsi.txt b/tools/quick_dump/vlv_flisdsi.txt
new file mode 100644
index 0000000..18f2b00
--- /dev/null
+++ b/tools/quick_dump/vlv_flisdsi.txt
@@ -0,0 +1,39 @@
+('MIPI4DPHY_RCOMP_IOSFSB_REG0', '0x0000', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG1', '0x0001', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG2', '0x0002', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG3', '0x0003', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG4', '0x0004', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG5', '0x0005', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG6', '0x0006', 'FLISDSI')
+('MIPI4DPHY_RCOMP_IOSFSB_REG7', '0x0007', 'FLISDSI')
+('DSI_CFG', '0x0008', 'FLISDSI')
+('DSI_DLLCOUNTCD_STATUS', '0x0009', 'FLISDSI')
+('DSI_RXCDCNTRL', '0x000a', 'FLISDSI')
+('DSI_HSRCOMP_STAT', '0x000b', 'FLISDSI')
+('DSI_LPRCOMP_STAT', '0x000c', 'FLISDSI')
+('DSI_LPRCOMP2', '0x000d', 'FLISDSI')
+('DSI_LPRCOMP1', '0x000e', 'FLISDSI')
+('DSI_BGCTL', '0x000f', 'FLISDSI')
+('DSI_RCCCFG', '0x0010', 'FLISDSI')
+('DSI_MISRDOUTLP', '0x0011', 'FLISDSI')
+('DSI_RCCRCOMP', '0x0012', 'FLISDSI')
+('DSI_BSCOMPARE', '0x0013', 'FLISDSI')
+('DSI_RCOMPCTL1', '0x0014', 'FLISDSI')
+('DSI_TXCNTRL', '0x0015', 'FLISDSI')
+('DSI_MISRDOUT1', '0x0016', 'FLISDSI')
+('DSI_DLLCTL2', '0x0017', 'FLISDSI')
+('DSI_DLLCTL1', '0x0018', 'FLISDSI')
+('DSI_ACIOCFG2', '0x0019', 'FLISDSI')
+('DSI_ACIOCFG1', '0x001a', 'FLISDSI')
+('DSI_ACIOSS', '0x001b', 'FLISDSI')
+('DSI_ACIOERR1', '0x001c', 'FLISDSI')
+('DSI_ACIOERR2', '0x001d', 'FLISDSI')
+('DSI_MISRDOUT2', '0x001e', 'FLISDSI')
+('DSI_RCOMPCTL2', '0x001f', 'FLISDSI')
+('DSI_ALL01', '0x0020', 'FLISDSI')
+('DSI_DLLCTL3', '0x0021', 'FLISDSI')
+('DSI_DATAEYE1', '0x0022', 'FLISDSI')
+('DSI_DATAEYE2', '0x0023', 'FLISDSI')
+('DSI_DATAEYE3', '0x0024', 'FLISDSI')
+('DSI_DATAEYE4', '0x0025', 'FLISDSI')
+('DSI_DATAEYE5', '0x0026', 'FLISDSI')
--
1.8.4
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