On Mon, May 19, 2014 at 02:47:20PM +0300, Ville Syrjälä wrote: > On Mon, May 19, 2014 at 04:28:58PM +0530, sourab.gupta@xxxxxxxxx wrote: > > From: Sourab Gupta <sourab.gupta@xxxxxxxxx> > > > > Using MMIO based flips on Gen5+ for Media power well residency optimization. > > The blitter ring is currently being used just for command streamer based > > flip calls. For pure 3D workloads, with MMIO flips, there will be no use > > of blitter ring and this will ensure the 100% residency for Media well. > > > > Can we address the condition for race between page flip mmio vs set base mmio > > in a seperate patch or do we address it in this patch only? In which case, this > > patch may be dependent on > > http://lists.freedesktop.org/archives/intel-gfx/2014-April/043759.html > > > > v2: The MMIO flips now use the interrupt driven mechanism for issuing the > > flips when target seqno is reached. (Incorporating Ville's idea) > > > > v3: Rebasing on latest code. Code restructuring after incorporating > > Damien's comments > > > > v4: Addressing Ville's review comments > > -general cleanup > > -updating only base addr instead of calling update_primary_plane > > -extending patch for gen5+ platforms > > > > v5: Addressed Ville's review comments > > -Making mmio flip vs cs flip selection based on module parameter > > -Adding check for DRIVER_MODESET feature in notify_ring before calling > > notify mmio flip. > > -Other changes mostly in function arguments > > > > Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx> > > Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/i915_dma.c | 1 + > > drivers/gpu/drm/i915/i915_drv.h | 6 ++ > > drivers/gpu/drm/i915/i915_gem.c | 2 +- > > drivers/gpu/drm/i915/i915_irq.c | 3 + > > drivers/gpu/drm/i915/i915_params.c | 4 ++ > > drivers/gpu/drm/i915/intel_display.c | 113 +++++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/i915/intel_drv.h | 6 ++ > > 7 files changed, 134 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > > index 46f1dec..672c28f 100644 > > --- a/drivers/gpu/drm/i915/i915_dma.c > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > @@ -1570,6 +1570,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) > > spin_lock_init(&dev_priv->backlight_lock); > > spin_lock_init(&dev_priv->uncore.lock); > > spin_lock_init(&dev_priv->mm.object_stat_lock); > > + spin_lock_init(&dev_priv->mmio_flip_lock); > > dev_priv->ring_index = 0; > > mutex_init(&dev_priv->dpio_lock); > > mutex_init(&dev_priv->modeset_restore_lock); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 4006dfe..9f1d042 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1543,6 +1543,8 @@ struct drm_i915_private { > > struct i915_ums_state ums; > > /* the indicator for dispatch video commands on two BSD rings */ > > int ring_index; > > + /* protects the mmio flip data */ > > + spinlock_t mmio_flip_lock; > > }; > > > > static inline struct drm_i915_private *to_i915(const struct drm_device *dev) > > @@ -2019,6 +2021,7 @@ struct i915_params { > > bool reset; > > bool disable_display; > > bool disable_vtd_wa; > > + bool use_mmio_flip; > > }; > > extern struct i915_params i915 __read_mostly; > > > > @@ -2209,6 +2212,7 @@ bool i915_gem_retire_requests(struct drm_device *dev); > > void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); > > int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, > > bool interruptible); > > +int i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno); > > static inline bool i915_reset_in_progress(struct i915_gpu_error *error) > > { > > return unlikely(atomic_read(&error->reset_counter) > > @@ -2580,6 +2584,8 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, > > int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, > > struct drm_file *file); > > > > +void intel_notify_mmio_flip(struct intel_ring_buffer *ring); > > + > > /* overlay */ > > extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); > > extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > > index fa5b5ab..5b4e953 100644 > > --- a/drivers/gpu/drm/i915/i915_gem.c > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > @@ -975,7 +975,7 @@ i915_gem_check_wedge(struct i915_gpu_error *error, > > * Compare seqno against outstanding lazy request. Emit a request if they are > > * equal. > > */ > > -static int > > +int > > i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) > > { > > int ret; > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index b10fbde..31e98e2 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -1084,6 +1084,9 @@ static void notify_ring(struct drm_device *dev, > > > > trace_i915_gem_request_complete(ring); > > > > + if (drm_core_check_feature(dev, DRIVER_MODESET)) > > + intel_notify_mmio_flip(ring); > > + > > I'm not a fan of such checks. > > After a bit of extra thought I got the idea of adding a per-ring > notify_list. So we could have something like this: > > struct ring_notify { > void (*notify)(struct ring_notify *notify); > struct list_head list; > u32 seqno; > }; > > intel_crtc { > ... > struct ring_notify mmio_flip_notify; > ... > }; > > I'll probably want something like this for FBC as well, so I guess > we might as well add it from the start. I think you could do this > as two patches; first one adds the ring notify list, second one > implements the mmio flip on top. This fells like massive overkill, at least for now. So imo the check is ok. What I do wonder about is whether we really want to run this in interrupt context. With atomic sprite updates we need to do the vblank avoidance, and that really shouldn't happen from interrupt context. So why can't we just latch a work item which uses all the established seqno waiting stuff and so avoids all these issues (and a pile of duplicated code)? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
