On Mon, May 19, 2014 at 07:56:11AM +0100, Chris Wilson wrote:
> This also appears to be true (but not documented as so) for gen4 and
> gen5. To generalise we force it into the low mappable region for all
> non-LLC platforms. If we locate the HWS at the top of the GTT the
> machine will hard hang during boot (fails on pnv, gm45, ilk and byt,
> but works on snb, ivb, hsw).
I take it this is the documented part?
"[DevBLB] Only:
Format = Bits 28:12 of graphics memory address (bits 31:29 MBZ)."
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index cb6d510245b5..9576b8f57150 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1362,6 +1362,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
> struct drm_i915_gem_object *obj;
>
> if ((obj = ring->status_page.obj) == NULL) {
> + unsigned flags;
> int ret;
>
> obj = i915_gem_alloc_object(ring->dev, 4096);
> @@ -1374,7 +1375,10 @@ static int init_status_page(struct intel_ring_buffer *ring)
> if (ret)
> goto err_unref;
>
> - ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
> + flags = 0;
> + if (!HAS_LLC(ring->dev))
> + flags |= PIN_MAPPABLE;
Maybe there should be a comment why we need PIN_MAPPABLE even though we
never map it?
> + ret = i915_gem_obj_ggtt_pin(obj, 0, flags);
Why the alignment change? Well, I guess it'll end up 4k aligned anyway
since it's not tiled.
> if (ret) {
> err_unref:
> drm_gem_object_unreference(&obj->base);
> --
> 2.0.0.rc2
>
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--
Ville Syrjälä
Intel OTC
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