On Tue, May 13, 2014 at 05:46:31PM +0100, Damien Lespiau wrote: > On Tue, May 13, 2014 at 06:38:32PM +0200, Daniel Vetter wrote: > > > Doesn't work for me, I still have an underrun at boot-up. > > > > I'm at a loss tbh with ideas. We successfully disable both pipes, then > > enable pipe A and it all works. > > > > Then we enable pipe B and _both_ pipes underrun immediately afterwards. > > Really strange. Can you please reproduce the issue again on > > drm-intel-nightly (latest -nightly should also have the display > > corruptions fixed, so good to retest anyway) and attach a new dmesg with > > drm.debug=0xe. > > > > Meanwhile I'll try to come up with new theories and ideas. > > I do remember a reporter saying a BIOS upgrade fixed that for him. This > is one of the reasons Paulo put that BIOS update message. > > It's worth the try if you ask me (the BIOS update will bring new memory > latency values). The fifo underrun code should be able to cope with bios stupidity - that's why we don't enable it on takeover. Apparently there's a bug in that logic somewhere. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
