On Tue, May 13, 2014 at 01:25:49PM +0100, Chris Wilson wrote: > On Tue, May 13, 2014 at 02:02:07PM +0200, Daniel Vetter wrote: > > Somehow UXA submits a completely bogus DR4 value since essentially > > forever. It was originally introduced in > > > > commit bade7d7d2505a10a8a7d24b084aff9742e2d6d64 > > Author: Eric Anholt <eric@xxxxxxxxxx> > > Date: Fri Jun 6 14:03:25 2008 -0700 > > > > Use the DRM for submitting batchbuffers when available. > > > > and dutifully copied around ever since. Since we want to keep the > > general dirt catching around just special case the UXA value. > > > > This regression was introduced in > > > > commit 9cb346648d9c529eccc5c7f30093e82d37004e37 > > Author: Daniel Vetter <daniel.vetter@xxxxxxxx> > > Date: Thu Apr 24 08:09:11 2014 +0200 > > > > drm/i915: Catch dirt in unused execbuffer fields > > > > v2: Pimp commit message a bit and remove the double space. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78494 > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Jörg Otte <jrg.otte@xxxxxxxxx> > > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > > To be fair, it is a sensible value if one supposes a Region style API to > cliprects. Under that API, DR[14] define the extents of the clip region, > and ((0,0), (0,0)) [DR1==DR4==0] would mean all clipped, do not draw > anything. Hm right. I've added this to the commit message. > Anyway, as far as fixing up the EINVAL, > Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> And merged the patch to dinq. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
