On Fri, May 09, 2014 at 12:09:46PM +0300, Ville Syrjälä wrote: > On Fri, May 09, 2014 at 07:03:09AM +0100, Chris Wilson wrote: > > On Thu, May 08, 2014 at 07:23:15PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > The pipe might not start to actually run until the port has been enabled > > > (depends on the platform and port type). So don't try to wait for vblank > > > after we enabled the pipe but haven't yet enabled the port. > > > > I am pretty sure those waits were in the docs. Pretty sure, not certain > > though. > > I didn't find them anywhere. The only vblank waits I see are the ones > for gen2 between disabling the planes and the pipe since the pipe > disable isn't double buffered on vblank. And that wait is still there > due to intel_disable_primary_hw_plane(). If my mmio vs. CS flip race > series ever gets reviewed that also gets killed, but I do add back an > explicit vblank wait for gen2 only into i9xx_crtc_disable(). Right, there is only the explicit wait required for the panel scaler, as that more or less requires a sequence of writes to the double-buffered registers. Otherwise, the waits I remember are just warning that the register updates are double-buffered. So removing the waits for the pipe on seems a resonable thing. In the event that we enable then disable the pipe all within a single frame (i.e. before the enable register updates are written) this should still work as the next register update will take the disable values for the current request. I.e. I don't think we need to insert explicit waits between enable/disabled. Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
