On Thu, May 08, 2014 at 07:23:13PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Use the same code for enabling/disabling planes on all platforms. Rename
> the functions to reflect that they're no longer specific to any
> platform.
>
> For now we leave the plane enable/disable to ccur at the same old
> position in the modeset sequence.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 134 +++++++++++++++--------------------
> 1 file changed, 56 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c65e7f7..3ee4995 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3634,7 +3634,49 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
> hsw_enable_ips(intel_crtc);
> }
>
> -static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
> +static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
> +{
> + if (!enable && intel_crtc->overlay) {
> + struct drm_device *dev = intel_crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + mutex_lock(&dev->struct_mutex);
> + dev_priv->mm.interruptible = false;
> + (void) intel_overlay_switch_off(intel_crtc->overlay);
> + dev_priv->mm.interruptible = true;
> + mutex_unlock(&dev->struct_mutex);
> + }
> +
> + /* Let userspace switch the overlay on again. In most cases userspace
> + * has to recompute where to put it anyway.
> + */
> +}
> +
> +/**
> + * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
> + * cursor plane briefly if not already running after enabling the display
> + * plane.
> + * This workaround avoids occasional blank screens when self refresh is
> + * enabled.
> + */
> +static void
> +g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
> +{
> + u32 cntl = I915_READ(CURCNTR(pipe));
> +
> + if ((cntl & CURSOR_MODE) == 0) {
> + u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
> +
> + I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
> + I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
> + intel_wait_for_vblank(dev_priv->dev, pipe);
> + I915_WRITE(CURCNTR(pipe), cntl);
> + I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
> + I915_WRITE(FW_BLC_SELF, fw_bcl_self);
> + }
> +}
> +
> +static void intel_crtc_enable_planes(struct drm_crtc *crtc)
i9xx_crtc_enable_planes might have been better, given Damien's pet
project. But otoh we might just want to switch to doing a generic atomic
pageflip across all planes before we call down into crtc_disable hooks
(and the reverse after crtc_enable), so meh ;-)
-Daniel
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3644,7 +3686,11 @@ static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
>
> intel_enable_primary_hw_plane(dev_priv, plane, pipe);
> intel_enable_planes(crtc);
> + /* The fixup needs to happen before cursor is enabled */
> + if (IS_G4X(dev))
> + g4x_fixup_plane(dev_priv, pipe);
> intel_crtc_update_cursor(crtc, true);
> + intel_crtc_dpms_overlay(intel_crtc, true);
>
> hsw_enable_ips(intel_crtc);
>
> @@ -3653,7 +3699,7 @@ static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
> mutex_unlock(&dev->struct_mutex);
> }
>
> -static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
> +static void intel_crtc_disable_planes(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3669,6 +3715,7 @@ static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
>
> hsw_disable_ips(intel_crtc);
>
> + intel_crtc_dpms_overlay(intel_crtc, false);
> intel_crtc_update_cursor(crtc, false);
> intel_disable_planes(crtc);
> intel_disable_primary_hw_plane(dev_priv, plane, pipe);
> @@ -3726,7 +3773,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> if (HAS_PCH_CPT(dev))
> cpt_verify_modeset(dev, intel_crtc->pipe);
>
> - ilk_crtc_enable_planes(crtc);
> + intel_crtc_enable_planes(crtc);
>
> /*
> * There seems to be a race in PCH platform hw (at least on some
> @@ -3829,7 +3876,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> /* If we change the relative order between pipe/planes enabling, we need
> * to change the workaround. */
> haswell_mode_set_planes_workaround(intel_crtc);
> - ilk_crtc_enable_planes(crtc);
> + intel_crtc_enable_planes(crtc);
>
> drm_vblank_on(dev, pipe);
> }
> @@ -3861,7 +3908,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> if (!intel_crtc->active)
> return;
>
> - ilk_crtc_disable_planes(crtc);
> + intel_crtc_disable_planes(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
> @@ -3924,7 +3971,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (!intel_crtc->active)
> return;
>
> - ilk_crtc_disable_planes(crtc);
> + intel_crtc_disable_planes(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> intel_opregion_notify_encoder(encoder, false);
> @@ -3970,48 +4017,6 @@ static void haswell_crtc_off(struct drm_crtc *crtc)
> intel_ddi_put_crtc_pll(crtc);
> }
>
> -static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
> -{
> - if (!enable && intel_crtc->overlay) {
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - mutex_lock(&dev->struct_mutex);
> - dev_priv->mm.interruptible = false;
> - (void) intel_overlay_switch_off(intel_crtc->overlay);
> - dev_priv->mm.interruptible = true;
> - mutex_unlock(&dev->struct_mutex);
> - }
> -
> - /* Let userspace switch the overlay on again. In most cases userspace
> - * has to recompute where to put it anyway.
> - */
> -}
> -
> -/**
> - * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
> - * cursor plane briefly if not already running after enabling the display
> - * plane.
> - * This workaround avoids occasional blank screens when self refresh is
> - * enabled.
> - */
> -static void
> -g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
> -{
> - u32 cntl = I915_READ(CURCNTR(pipe));
> -
> - if ((cntl & CURSOR_MODE) == 0) {
> - u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
> -
> - I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
> - I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
> - intel_wait_for_vblank(dev_priv->dev, pipe);
> - I915_WRITE(CURCNTR(pipe), cntl);
> - I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
> - I915_WRITE(FW_BLC_SELF, fw_bcl_self);
> - }
> -}
> -
> static void i9xx_pfit_enable(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -4315,7 +4320,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
> bool is_dsi;
>
> WARN_ON(!crtc->enabled);
> @@ -4347,11 +4351,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> intel_wait_for_vblank(dev_priv->dev, pipe);
> intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
>
> - intel_enable_primary_hw_plane(dev_priv, plane, pipe);
> - intel_enable_planes(crtc);
> - intel_crtc_update_cursor(crtc, true);
> -
> - intel_update_fbc(dev);
> + intel_crtc_enable_planes(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->enable(encoder);
> @@ -4366,7 +4366,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
>
> WARN_ON(!crtc->enabled);
>
> @@ -4390,17 +4389,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> intel_wait_for_vblank(dev_priv->dev, pipe);
> intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
>
> - intel_enable_primary_hw_plane(dev_priv, plane, pipe);
> - intel_enable_planes(crtc);
> - /* The fixup needs to happen before cursor is enabled */
> - if (IS_G4X(dev))
> - g4x_fixup_plane(dev_priv, pipe);
> - intel_crtc_update_cursor(crtc, true);
> -
> - /* Give the overlay scaler a chance to enable if it's on this pipe */
> - intel_crtc_dpms_overlay(intel_crtc, true);
> -
> - intel_update_fbc(dev);
> + intel_crtc_enable_planes(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->enable(encoder);
> @@ -4430,7 +4419,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
>
> if (!intel_crtc->active)
> return;
> @@ -4438,17 +4426,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
>
> - /* Give the overlay scaler a chance to disable if it's on this pipe */
> - intel_crtc_wait_for_pending_flips(crtc);
> - drm_vblank_off(dev, pipe);
> -
> - if (dev_priv->fbc.plane == plane)
> - intel_disable_fbc(dev);
> -
> - intel_crtc_dpms_overlay(intel_crtc, false);
> - intel_crtc_update_cursor(crtc, false);
> - intel_disable_planes(crtc);
> - intel_disable_primary_hw_plane(dev_priv, plane, pipe);
> + intel_crtc_disable_planes(crtc);
>
> intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
> intel_disable_pipe(dev_priv, pipe);
> --
> 1.8.3.2
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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