On Fri, May 09, 2014 at 02:59:42PM +0300, Ville Syrjälä wrote: > On Sun, Mar 23, 2014 at 02:31:05PM +0530, sourab.gupta@xxxxxxxxx wrote: > > + intel_do_mmio_flip(dev, crtc); > > + mmio_flip_data->seqno = 0; > > + ring->irq_put(ring); > > + } > > + } > > + > > + spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); > > +} > > + > > +/* Using MMIO based flips starting from VLV, for Media power well > > + * residency optimization. The other alternative of having Render > > + * ring based flip calls is not being used, as the performance > > + * (FPS) of certain 3D Apps was getting severly affected. > > + */ > > +static int intel_gen7_queue_mmio_flip(struct drm_device *dev, > > + struct drm_crtc *crtc, > > + struct drm_framebuffer *fb, > > + struct drm_i915_gem_object *obj, > > + uint32_t flags) > > There's nothing gen7 specific here. So you could just rename the > function to eg. intel_queue_mmio_flip(). Maybe also move the > comment about VLV to where you set up the function pointer. Actually this code isn't entirely gen agnostic. It should work on gen5+ since all of those have a flip done interrupt. For older platforms we use some clever tricks involving the flip_pending status bits and vblank irqs. That code won't work for mmio flips. We'd need to add another way to complete the flips based. That would involve using the frame counter to make it accurate. To avoid races there we'd definitely need to use the vblank evade mechanism to make sure we sample the frame counter within the same frame as when we write the registers. Also gen2 has the extra complication that it lacks a hardware frame counter. So I think we can start off with limiting this to gen5+, and later we can extend it to cover the older platforms since we anyway need to do that work to get the nuclear flips working. BTW I gave this code a whirl on my IVB and everything seems to work fine. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
