UXA was reporting page-flip completion as soon as the flip was scheduled
with the kernel, instead of waiting for the kernel to indicate that the
flip had actually completed.
Moving the DRI2SwapComplete call to the right place fixes all of our
Piglit tests for OML_sync_control when run on xf86-video-intel/UXA,
aside from a bit of difficult-to-reproduce flakiness when using a
divisor > 1.
This also eliminates a compile-time and run-time warning when built
against an xserver with "Warn on DRI2SwapComplete with constant UST/MSC"
applied.
Signed-off-by: Jamey Sharp <jamey@xxxxxxxxxxx>
Cc: Theo Hill <Theo0x48@xxxxxxxxx>
Cc: Eric Anholt <eric@xxxxxxxxxx>
---
src/uxa/intel_dri.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/uxa/intel_dri.c b/src/uxa/intel_dri.c
index ca58052..3745767 100644
--- a/src/uxa/intel_dri.c
+++ b/src/uxa/intel_dri.c
@@ -932,10 +932,6 @@ I830DRI2ScheduleFlip(struct intel_screen_private *intel,
/* Then flip DRI2 pointers and update the screen pixmap */
I830DRI2ExchangeBuffers(intel, info->front, info->back);
- DRI2SwapComplete(info->client, draw, 0, 0, 0,
- DRI2_EXCHANGE_COMPLETE,
- info->event_complete,
- info->event_data);
return TRUE;
}
@@ -1090,6 +1086,12 @@ void I830DRI2FlipEventHandler(unsigned int frame, unsigned int tv_sec,
assert(intel->pending_flip[flip_info->pipe] == flip_info);
intel->pending_flip[flip_info->pipe] = NULL;
+ DRI2SwapComplete(flip_info->client, drawable,
+ frame, tv_sec, tv_usec,
+ DRI2_EXCHANGE_COMPLETE,
+ flip_info->event_complete,
+ flip_info->event_data);
+
chain = flip_info->chain;
if (chain) {
DrawablePtr chain_drawable = NULL;
--
1.9.2
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