On Tue, May 06, 2014 at 10:21:36PM -0700, Ben Widawsky wrote: > There is a good debate to be had about how best to fit the aliasing > PPGTT into the code. However, as it stands right now, getting aliasing > PPGTT bindings is a hack, and done through implicit arguments. To make > this absolutely clear, WARN and return an error if a driver writer tries > to do something they shouldn't. > > I have no issue with an eventual revert of this patch. It makes sense > for what we have today. > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_gem.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 1567911..c54668c 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3877,9 +3877,13 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj, > uint32_t alignment, > unsigned flags) > { > + struct drm_i915_private *dev_priv = obj->base.dev->dev_private; > struct i915_vma *vma; > int ret; > > + if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) > + return -ENODEV; > + > if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) > return -EINVAL; > > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx