On Tue, May 06, 2014 at 10:21:30PM -0700, Ben Widawsky wrote: > It was always the intention to do the topdown allocation for context > objects (Chris' idea originally). Unfortunately, I never managed to land > the patch, but someone else did, so now we can use it. > > As a reminder, hardware contexts never need to be in the precious GTT > aperture space - which is what is what happens with the normal bottom up > allocation we do today. Doing a top down allocation increases the odds > that the HW contexts can get out of the way, especially with per FD > contexts as is done in full PPGTT > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index f6354e0..66fcfc9 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1035,8 +1035,7 @@ alloc: > &ppgtt->node, GEN6_PD_SIZE, > GEN6_PD_ALIGN, 0, > 0, dev_priv->gtt.base.total, > - DRM_MM_SEARCH_DEFAULT, > - DRM_MM_CREATE_DEFAULT); > + DRM_MM_TOPDOWN); > if (ret == -ENOSPC && !retried) { > ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, > GEN6_PD_SIZE, GEN6_PD_ALIGN, > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx