From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 9 +++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e70a9f0..3966ff2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1318,6 +1318,7 @@ struct drm_i915_private {
u32 gt_irq_mask;
u32 pm_irq_mask;
u32 pm_rps_events;
+ u32 pm_rps_freq_req;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct work_struct hotplug_work;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6af51ad..3e8bcca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1162,7 +1162,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj > 0)
adj *= 2;
else
- adj = 1;
+ adj = dev_priv->pm_rps_freq_req;
new_delay = dev_priv->rps.cur_freq + adj;
/*
@@ -1181,7 +1181,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj < 0)
adj *= 2;
else
- adj = -1;
+ adj = -1 * dev_priv->pm_rps_freq_req;
new_delay = dev_priv->rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv->rps.cur_freq;
@@ -4088,6 +4088,11 @@ void intel_irq_init(struct drm_device *dev)
/* Let's track the enabled rps events */
dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+ if (IS_CHERRYVIEW(dev))
+ dev_priv->pm_rps_freq_req = CHV_GPU_FREQ_REQ;
+ else
+ dev_priv->pm_rps_freq_req = GEN6_GPU_FREQ_REQ;
+
setup_timer(&dev_priv->gpu_error.hangcheck_timer,
i915_hangcheck_elapsed,
(unsigned long) dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ff34c4..4998d6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -529,6 +529,9 @@ enum punit_power_well {
#define CHV_FB_RPE_FREQ_SHIFT 8
#define CHV_FB_RPE_FREQ_MASK 0xff
+#define CHV_GPU_FREQ_REQ 2
+#define GEN6_GPU_FREQ_REQ 1
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
--
1.9.1
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