On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Chon Ming Lee <chon.ming.lee@xxxxxxxxx>
>
> With additional of pipe C, current 1 bit registers for pipe select
> for HDMI and DP are no longer able to gather for 3 pipes. As a result,
> new bits location in the same registers are added.
>
> For HDMI, VLV uses bit 30, CHV uses bit 24-25.
>
> For DP, VLV uses bit 30, CHV uses bit 16-17.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@xxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_display.c | 6 ++++++
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
> 4 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 75f31f5..91c8fac 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2478,6 +2478,10 @@ enum punit_power_well {
> #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
> #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
>
> +/* CHV SDVO/HDMI bits: */
> +#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
> +#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
> +
>
> /* DVO port control */
> #define DVOA 0x61120
> @@ -3235,6 +3239,8 @@ enum punit_power_well {
> #define DP_PORT_EN (1 << 31)
> #define DP_PIPEB_SELECT (1 << 30)
> #define DP_PIPE_MASK (1 << 30)
> +#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
> +#define DP_PIPE_MASK_CHV (3 << 16)
>
> /* Link training mode - select a suitable mode for each stage */
> #define DP_LINK_TRAIN_PAT_1 (0 << 28)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 36d6e212..f849c65 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1337,6 +1337,9 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
> u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
> if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
> return false;
> + } else if (IS_CHERRYVIEW(dev_priv->dev)) {
> + if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
> + return false;
> } else {
> if ((val & DP_PIPE_MASK) != (pipe << 30))
> return false;
> @@ -1353,6 +1356,9 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
> if (HAS_PCH_CPT(dev_priv->dev)) {
> if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
> return false;
> + } else if (IS_CHERRYVIEW(dev_priv->dev)) {
> + if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
> + return false;
> } else {
> if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
> return false;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 71a4fa2..21ac845 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -964,8 +964,12 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - if (crtc->pipe == 1)
> - intel_dp->DP |= DP_PIPEB_SELECT;
> + if (!IS_CHERRYVIEW(dev)) {
> + if (crtc->pipe == 1)
> + intel_dp->DP |= DP_PIPEB_SELECT;
> + } else {
> + intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
> + }
> } else {
> intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> }
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index bbda011..9f868f4 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -652,6 +652,8 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder)
>
> if (HAS_PCH_CPT(dev))
> hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> + else if (IS_CHERRYVIEW(dev))
> + hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
> else
> hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
>
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