Re: haswell's PIPE_CLK_SEL registers

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On Wed, Apr 30, 2014 at 01:55:37PM +1000, Dave Airlie wrote:
> The docs don't mention the regs
> 
> PIPE_CLK_SEL_A->C at 0x46140-46148, is there any more info on these of
> if they exist?

Attached.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
Title: PIPE_CLK_SEL
PIPE_CLK_SEL
Register Space: MMIO: 0/2/0
Project: DevHSW
Source: BSpec
Default Value: 0x00000000
Access: R/W
Size (in bits): 32
Address: 46140h-46143h
Name: Pipe A Clock Select
ShortName: PIPE_CLK_SEL_A
Unit: dcpr
Custom Display Category: NDE Clocks
Custom Display FUB: dcpr
Custom Display Partition: par1
Power: Always on
Reset: soft
Address: 46144h-46147h
Name: Pipe B Clock Select
ShortName: PIPE_CLK_SEL_B
Unit: dcpr
Custom Display Category: NDE Clocks
Custom Display FUB: dcpr
Custom Display Partition: par1
Power: Always on
Reset: soft
Address: 46148h-4614Bh
Name: Pipe C Clock Select
ShortName: PIPE_CLK_SEL_C
Unit: dcpr
Custom Display Category: NDE Clocks
Custom Display FUB: dcpr
Custom Display Partition: par1
Power: Always on
Reset: soft
This register maps the port clock to the pipe.
There is one instance of this register format per pipe A/B/C.
DWord Bit Description
0 31:29
Pipe Clock Select
Select which PLL to use for this pipe.
Pipe EDP always uses DDIA clock.
Value Name Description Project
000b None No PLL selected. Clock is disabled for this transcoder.  
010b DDIB Select DDIB clock  
011b DDIC Select DDIC clock  
100b DDID Select DDID clock DevHSW
100b Reserved Reserved. DDID is not supported for ULT and must not be selected. DevHSW:ULT
101b DDIE Select DDIE clock DevHSW, EXCLUDE(DevHSW:GT0:X0)
Others Reserved Reserved  
Restriction
Restriction : This must not be changed while the pipe is enabled.
28:0
Reserved
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