ville.syrjala@xxxxxxxxxxxxxxx writes:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The spec only tells us to set individual bits here and there. So we use
> RMW for most things. Do the same for the swing calc init.
>
> Eventually we should optimize things to just blast the final value in
> with group access whenever possible. But to do that someone needs to
> take a good look at what's the reset value for each registers, and
> possibly if the BIOS manages to frob with some of them. For now
> use RMW access always.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Some accesses use define masks, some hardcoded ones.
But as they were there to begin with, not a problem of
these patches.
For future work, I think we could get rid of
quite amount of DWXX_CHXX definitions if we
would build macros that setup the function,lane/group
and broadcast.
Patches 65 and 66,
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_dp.c | 17 ++++++++++++++---
> drivers/gpu/drm/i915/intel_hdmi.c | 18 ++++++++++++++----
> 3 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b91232f..7056994 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -698,6 +698,13 @@ enum punit_power_well {
> #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
> #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>
> +#define _VLV_PCS01_DW10_CH0 0x0228
> +#define _VLV_PCS23_DW10_CH0 0x0428
> +#define _VLV_PCS01_DW10_CH1 0x2628
> +#define _VLV_PCS23_DW10_CH1 0x2828
> +#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
> +#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
> +
> #define _VLV_PCS_DW11_CH0 0x822c
> #define _VLV_PCS_DW11_CH1 0x842c
> #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4c54930..9cbd702 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2346,7 +2346,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
> mutex_lock(&dev_priv->dpio_lock);
>
> /* Clear calc init */
> - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> + val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> + val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>
> /* Program swing deemph */
> for (i = 0; i < 4; i++) {
> @@ -2397,8 +2403,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
> }
>
> /* Start swing calculation */
> - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> - (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> + val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> + val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>
> /* LRC Bypass */
> val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e912554..d2b1186 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1283,7 +1283,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> /* FIXME: Fix up value only after power analysis */
>
> /* Clear calc init */
> - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> + val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> + val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>
> /* FIXME: Program the support xxx V-dB */
> /* Use 800mV-0dB */
> @@ -1322,9 +1328,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
> #endif
> /* Start swing calculation */
> - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> - DPIO_PCS_SWING_CALC_TX0_TX2 |
> - DPIO_PCS_SWING_CALC_TX1_TX3);
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> + val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> + val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>
> /* LRC Bypass */
> val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> --
> 1.8.3.2
>
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