On Mon, Apr 21, 2014 at 01:34:13PM +0530, deepak.s@xxxxxxxxxxxxxxx wrote:
> From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
>
> Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> [vsyrjala: Fix merge fubmle where the code ended up in
> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b37d108..fdb66aa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3831,7 +3831,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> GEN6_RP_UP_BUSY_AVG |
> GEN6_RP_DOWN_IDLE_AVG);
>
> + /* ToDo: Update the mem freq based on latest spec [CHV]*/
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> + switch ((val >> 6) & 3) {
> + case 0:
> + case 1:
> + case 2:
> + dev_priv->mem_freq = 1600;
> + break;
> + case 3:
> + dev_priv->mem_freq = 2000;
> + break;
> + }
>
> DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
This, like all the other patches related to freq. don't seem to be
findable by me. Seems fine for enabling
Acked-by: Ben Widawsky <ben@xxxxxxxxxxxx>
--
Ben Widawsky, Intel Open Source Technology Center
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