2014-04-09 7:28 GMT-03:00 <ville.syrjala@xxxxxxxxxxxxxxx>: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We implement the following workarounds: > * WaDisableAsyncFlipPerfMode:chv > * WaDisableSemaphoreAndSyncFlipWait:chv (at least partially) In the rebased version (on your gitorious tree, chv_rebase branch), the chunk for this WA got removed. I don't know if this was an accident or not. We need to, at least, fix the commit message. > * WaProgramMiArbOnOffAroundMiSetContext:chv > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_gem.c | 1 + > drivers/gpu/drm/i915/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > 3 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 84a7171..a9c33ec 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4376,6 +4376,7 @@ static int i915_gem_init_rings(struct drm_device *dev) > struct intel_ring_buffer *ring; > int i; > > + /* WaDisableSemaphoreAndSyncFlipWait:chv */ > for_each_ring(ring, dev_priv, i) > I915_WRITE(RING_RC_PSMI_CONTROL(ring), > _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index 28a2b15..142df90 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -606,7 +606,7 @@ mi_set_context(struct intel_ring_buffer *ring, > if (ret) > return ret; > > - /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */ > + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ Do we really need this WA for BDW and CHV? I couldn't find them on my docs for gen8... Thanks, Paulo > if (INTEL_INFO(ring->dev)->gen >= 7) > intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); > else > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 913b8ab..24022c5 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -581,7 +581,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) > * to use MI_WAIT_FOR_EVENT within the CS. It should already be > * programmed to '1' on all products. > * > - * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw > + * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv > */ > if (INTEL_INFO(dev)->gen >= 6) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
