From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Document the internal structure of the VLV display PHY a bit to help
people understand how the different register blocks relate to each
other.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0eff337..064e599 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -571,7 +571,45 @@ enum punit_power_well {
*
* DPIO is VLV only.
*
- * Note: digital port B is DDI0, digital pot C is DDI1
+ * Note: digital port B is DDI0, digital port C is DDI1
+ *
+ * Each display PHY is made up of one or two channels. Each channel
+ * houses a common lane part which contains the PLL and other common
+ * logic. CH0 common lane also contains the IOSF-SB logic for the
+ * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
+ * must be running when any DPIO registers are accessed.
+ *
+ * Eeach channel also has two splines, and each spline is made up of
+ * one Physical Access Coding Sub-Layer (PCS) block and two TX lanes.
+ * So each channel has two PCS blocks and four TX lanes. The TX lanes
+ * are used as DP lanes or TMDS data/clock pairs depending on the
+ * output type.
+ *
+ * Additionally the PHY also contains an AUX lane with AUX blocks
+ * for each channel. This is used for DP AUX communication, but
+ * this fact isn't really relevant for the driver since AUX is
+ * controlled from the display controller side. No DPIO registers
+ * need to be accessed during AUX communication,
+ *
+ * Generally the common lane corresponds to the pipe and
+ * the spline (PCS/TX) correponds to the port:
+ * pipe A == CMN/PLL/REF CH0
+ * pipe B == CMN/PLL/REF CH1
+ * port B == PCS/TX CH0
+ * port C == PCS/TX CH1
+ * This is especially important when we cross the streams
+ * ie. drive port B with pipe B, or port C with pipe A.
+ *
+ * ---------------------------------
+ * | CH0 | CH1 |
+ * | CMN/PLL/REF | CMN/PLL/REF |
+ * |---------------|---------------| Display PHY
+ * | PCS01 | PCS23 | PCS01 | PCS23 |
+ * |-------|-------|-------|-------|
+ * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
+ * ---------------------------------
+ * | DDI0 | DDI1 | DP/HDMI ports
+ * ---------------------------------
*/
#define DPIO_DEVFN 0
#define DPIO_OPCODE_REG_WRITE 1
--
1.8.3.2
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