With this all the pch encoder specific code is now gone from the
haswell ->crtc_disable function. Which finally readies the stage
for the last piece of all the hsw crt encoder rework, namely also
moving the SPLL disabling into the encoder post_disable function.
Which the next patch will do.
Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
---
drivers/gpu/drm/i915/intel_crt.c | 27 +++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 28 +---------------------------
drivers/gpu/drm/i915/intel_display.c | 4 ----
drivers/gpu/drm/i915/intel_drv.h | 2 +-
4 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 7a146f6d8c39..fd465bf7fd0d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -372,6 +372,31 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
I915_WRITE(_TRANSA_CHICKEN2, val);
}
+static void hsw_fdi_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ uint32_t val;
+
+ intel_ddi_post_disable(encoder);
+
+ val = I915_READ(_FDI_RXA_CTL);
+ val &= ~FDI_RX_ENABLE;
+ I915_WRITE(_FDI_RXA_CTL, val);
+
+ val = I915_READ(_FDI_RXA_MISC);
+ val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+ val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
+ I915_WRITE(_FDI_RXA_MISC, val);
+
+ val = I915_READ(_FDI_RXA_CTL);
+ val &= ~FDI_PCDCLK;
+ I915_WRITE(_FDI_RXA_CTL, val);
+
+ val = I915_READ(_FDI_RXA_CTL);
+ val &= ~FDI_RX_PLL_ENABLE;
+ I915_WRITE(_FDI_RXA_CTL, val);
+}
+
static void hsw_crt_post_disable(struct intel_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
@@ -380,6 +405,8 @@ static void hsw_crt_post_disable(struct intel_encoder *encoder)
lpt_disable_pch_transcoder(dev_priv);
intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
+
+ hsw_fdi_disable(encoder);
}
static void intel_enable_crt(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4fde38a253f0..9d455967e27b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1131,7 +1131,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
}
}
-static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
+void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -1317,32 +1317,6 @@ void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
udelay(600);
}
-void intel_ddi_fdi_disable(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
- struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- uint32_t val;
-
- intel_ddi_post_disable(intel_encoder);
-
- val = I915_READ(_FDI_RXA_CTL);
- val &= ~FDI_RX_ENABLE;
- I915_WRITE(_FDI_RXA_CTL, val);
-
- val = I915_READ(_FDI_RXA_MISC);
- val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
- val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
- I915_WRITE(_FDI_RXA_MISC, val);
-
- val = I915_READ(_FDI_RXA_CTL);
- val &= ~FDI_PCDCLK;
- I915_WRITE(_FDI_RXA_CTL, val);
-
- val = I915_READ(_FDI_RXA_CTL);
- val &= ~FDI_RX_PLL_ENABLE;
- I915_WRITE(_FDI_RXA_CTL, val);
-}
-
static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b370817f787f..728b5a25cb80 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3839,10 +3839,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (encoder->post_disable)
encoder->post_disable(encoder);
- if (intel_crtc->config.has_pch_encoder) {
- intel_ddi_fdi_disable(crtc);
- }
-
intel_crtc->active = false;
intel_update_watermarks(crtc);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5b8e34c6907e..77414333804a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -687,7 +687,7 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc);
void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
-void intel_ddi_fdi_disable(struct drm_crtc *crtc);
+void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config);
--
1.8.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
