On Fri, Apr 18, 2014 at 04:35:02PM +0300, Imre Deak wrote:
> This will be needed by the VLV runtime PM helpers too, so factor it out.
>
> Also add a safety check for the case where the previous force-off is
> still pending, since I'm not sure if Punit can handle a new setting
> while the previous one hasn't settled yet.
>
> v2:
> - unchanged
> v3:
> - add a note to the commit message about the safety check (Ville)
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 37 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 16 ++--------------
> 3 files changed, 40 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1f88917..795caea 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -905,6 +905,43 @@ static void hsw_runtime_resume(struct drm_i915_private *dev_priv)
> hsw_disable_pc8(dev_priv);
> }
>
> +int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
> +{
> + u32 val;
> + int err;
> +
> + val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
> + WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
> +
> +#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
> + /* Wait for a previous force-off to settle */
> + if (force_on) {
> + err = wait_for(!COND, 5);
> + if (err) {
> + DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
> + I915_READ(VLV_GTLC_SURVIVABILITY_REG));
> + return err;
> + }
> + }
> +
> + val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
> + val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
> + if (force_on)
> + val |= VLV_GFX_CLK_FORCE_ON_BIT;
> + I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
> +
> + if (!force_on)
> + return 0;
> +
> + err = wait_for(COND, 5);
> + if (err)
> + DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
> + I915_READ(VLV_GTLC_SURVIVABILITY_REG));
> +
> + return err;
> +#undef COND
> +}
> +
> static int intel_runtime_suspend(struct device *device)
> {
> struct pci_dev *pdev = to_pci_dev(device);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5254f4b..3cac434 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1968,6 +1968,7 @@ extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
> extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
> extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
> +int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
>
> extern void intel_console_resume(struct work_struct *work);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c45e5c1..d64ac32 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3129,16 +3129,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> /* Mask turbo interrupt so that they will not come in between */
> I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
>
> - /* Bring up the Gfx clock */
> - I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
> - I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
> - VLV_GFX_CLK_FORCE_ON_BIT);
> -
> - if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
> - I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
> - DRM_ERROR("GFX_CLK_ON request timed out\n");
> - return;
> - }
> + vlv_force_gfx_clock(dev_priv, true);
>
> dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
>
> @@ -3149,10 +3140,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> & GENFREQSTATUS) == 0, 5))
> DRM_ERROR("timed out waiting for Punit\n");
>
> - /* Release the Gfx clock */
> - I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
> - I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
> - ~VLV_GFX_CLK_FORCE_ON_BIT);
> + vlv_force_gfx_clock(dev_priv, false);
>
> I915_WRITE(GEN6_PMINTRMSK,
> gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
> --
> 1.8.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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