[QA] Testing report for DisplayPort Link Layer Compliance Test with HSW on ww16

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Summary

We finished the DisplayPort Link Layer Compliance Test on Haswell/Baytrail/Broadwell including: LL CTS for Testing Transmitter DUT on DPR-100 and LL Extension Test Set A for Testing Transmitter DUT on DPR-120.

This testing round have no changing result on HSW compared with last round.

Test Environment

 

64-bit HSW

64-bit BYT

64-bit BDW

Platform 

Shark Bay Desktop

Bayley Bay EV

Broadwell 

Processor

Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz

Intel Celeron N2820 @2.13GHz

Intel(R) CPU 0000 @ 1.20GHz(D0)

CRB

Flathead Creek

CRB FAB3 Rev03

STP FAB3

Bios version

HSWLPTU1.86C.0134.R00.1310022130

BBAYCRB1.X64.0078.R20.1401131845

BDW-E1R1.86C.0069.R00.1403240209

Kernel

(drm-intel-nightly) 8c7da4ebd7c0aa6f24a558634f6f59204cf65c0b

(drm-intel-nightly) 8c7da4ebd7c0aa6f24a558634f6f59204cf65c0b

(drm-intel-nightly) 8c7da4ebd7c0aa6f24a558634f6f59204cf65c0b

 

Test Result:

       All test cases reference from VESA® DisplayPort® Link Layer Compliance Test Specification. x

Detailed testing result attached as HTML format with the mail.

         DPR-120, it is HBR2 and MST capable Reference Sink and Branch device. It supports set of LL Ext A +(B) compliance tests (HBR2 extensions) to test DP Source.

LL CTS for Testing Transmitter DUT with DPR-100

Test Reference

Test Name

HSW

BYT

BDW

 

PASS/FAIL/SKIP

10/18/7

9/17/7

10/18/7

(4.2.1.1)

Source DUT Retry on No-Reply During Aux Read after Hot Plug Event

Pass

Pass

Pass

(4.2.1.2)

Source Retry on Invalid Reply During Aux Read after Hot Plug Event

Fail

Fail

Fail

(4.2.2.1)

EDID Read upon Hot Plug Event

Pass

Pass

Pass

(4.2.2.2)

DPCD Receiver Capability Read upon Hot Plug Event

Fail

Fail

Fail

(4.2.2.3)

EDID Read

Fail

Fail

Fail

(4.2.2.4)

EDID Read failure #1: I2C-Over-AUX NACK

Pass

Pass

Pass

(4.2.2.5)

EDID Read failure #2: I2C-Over-AUX DEFER

Fail

Fail

Fail

(4.2.2.6)

EDID Corruption Detection

Fail

Fail

Fail

(4.2.2.7)

Branch Device Detection upon HPD Plug Event

Fail

Fail

Fail

(4.2.2.8)

EDID read on IRQ_HPD event after Branch Device detection

Pass

Pass

Pass

(4.2.2.9)

E-DDC Four Block EDID Read

Skip

Skip

Skip

(4.3.1.1)

Successful Link Training Upon HPD Plug Event

Pass

Pass

Pass

(4.3.1.2)

Successful Link Training at All Supported Lane Counts and Link Speeds

Pass

Pass

Pass

(4.3.1.3)

Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence

Pass

Fail

Fail

(4.3.1.4)

Successful Link Training to a Lower Link Rate #1: Iterate at Maximum Voltage Swing

Skip

Skip

Skip

(4.3.1.5)

Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing

Skip

Skip

Skip

(4.3.1.6)

Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence

Fail

Fail

Pass

(4.3.1.7)

Successful Link Training at Lower Link Rate due to Loss of Symbol Lock During Channel Equalization Sequence

Pass

Pass

Pass

(4.3.1.8)

Unsuccessful Link Training at Lower Link Rate #1: Iterate at Maximum Voltage Swing

Fail

Fail

Fail

(4.3.1.9)

Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing

Fail

Fail

Fail

(4.3.1.10)

Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5)

Fail

Fail

Fail

(4.3.2.1)

Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock

Fail

Fail

Fail

(4.3.2.2)

Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock

Fail

Fail

Fail

(4.3.2.3)

Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock

Skip

Skip

Skip

(4.3.2.4)

Handling of IRQ HPD Pulse With No Error Status Bits Set

Fail

Fail

Fail

(4.3.2.5)

Lane Count Reduction

Skip

Skip

Skip

(4.3.2.6)

Lane Count Increase

Skip

Skip

Skip

(4.3.3.1)

Video Time Stamp Generation

Fail

Fail

Fail

(4.4.1.1)

Pixel Data Packing and Steering

Fail

Fail

Fail

(4.4.1.2)

Main Stream Data Packing and Stuffing ? Least Packed TU

Fail

Fail

Fail

(4.4.1.3)

Main Stream Data Packing and Stuffing ? Most Packed TU

Fail

Fail

Fail

(4.4.2)

Main Video Stream Format Change Handling

Skip

Skip

Skip

(4.4.3)

Power Management

Fail

Fail

Fail

(7.1.1.1)

Additional DPCD Handling Test 1

Pass

Pass

Pass

(7.1.1.2)

Additional DPCD Handling Test 2

Pass

Pass

Pass

     

Link Layer Extension Test Set A for Testing Transmitter DUT with DPR-120

Test Reference

Test Name

HSW

BYT

BDW

 

PASS/FAIL/SKIP

2/7/0

1/8/0

2/7/0

(400.3.1.1)

Successful Link Training at All Supported Lane Counts and Link Speeds: HBR2 Extension

Pass

Pass

Pass

(400.3.1.2)

Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension

Pass

Fail

Fail

(400.3.1.3)

Successful Link Training to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

Fail

Fail

Fail

(400.3.1.4)

Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

Fail

Fail

Fail

(400.3.1.5)

Successful Link Training with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence

Fail

Fail

Pass

(400.3.1.6)

Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension

Fail

Fail

Fail

(400.3.1.7)

Unsuccessful Link Training at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

Fail

Fail

Fail

(400.3.1.8)

Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

Fail

Fail

Fail

(400.3.1.9)

Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5): HBR2 Extension

Fail

Fail

Fail

 

 

Best Regards~~

 

Open Source Technology Center (OTC)

Terence Yang（杨光）

Tel: 86-021-61167360

iNet: 8821-7360

 

 

From: Yang, Guang A
Sent: Wednesday, February 26, 2014 2:06 PM
To: Barnes, Jesse; Widawsky, Benjamin; Theurer, Bruce M; Hockemeier, Steven J; Vetter, Daniel; Parenteau, Paul A; Jin, Gordon; Previte, Todd A; Bhat, Kiran U
Cc: Guo, JinxianX; OTC GFX QA Extended; He, Shuang; Sun, Yi
Subject: [QA] Testing report for DisplayPort Link Layer Compliance Test with HSW on ww09

 

Summary

We finished the DisplayPort Link Layer Compliance Test on Haswell including: LL CTS for Testing Transmitter DUT on DPR-100 and LL Extension Test Set A for Testing Transmitter DUT on DPR-120.

Test Environment

         Hardware

 

64-bit HSW

Platform 

Shark Bay Desktop

Processor

Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz

CRB

Flathead Creek

Software

 

64-bit HSW

Bios version

HSWLPTU1.86C.0134.R00.1310022130

Kernel

(drm-intel-nightly) 1be8f2b4dd6d3db00af24d4891c82d2650bd282d

Linux distribution

Fedora 19

 

Test Result:

       All test cases reference from VESA® DisplayPort® Link Layer Compliance Test Specification.

Detailed testing result attached as HTML format with the mail.

         DPR-120, it is HBR2 and MST capable Reference Sink and Branch device. It supports set of LL Ext A +(B) compliance tests (HBR2 extensions) to test DP Source.

LL CTS for Testing Transmitter DUT with DPR-100

Total:33/Pass:8/Fail:18/Skip:7

Test Reference

Test Name

Result

(4.2.1.1)

Source DUT Retry on No-Reply During Aux Read after Hot Plug Event

Pass

(4.2.1.2)

Source Retry on Invalid Reply During Aux Read after Hot Plug Event

Fail

(4.2.2.1)

EDID Read upon Hot Plug Event

Pass

(4.2.2.2)

DPCD Receiver Capability Read upon Hot Plug Event

Fail

(4.2.2.3)

EDID Read

Fail

(4.2.2.4)

EDID Read failure #1: I2C-Over-AUX NACK

Pass

(4.2.2.5)

EDID Read failure #2: I2C-Over-AUX DEFER

Fail

(4.2.2.6)

EDID Corruption Detection

Fail

(4.2.2.7)

Branch Device Detection upon HPD Plug Event

Fail

(4.2.2.8)

EDID read on IRQ_HPD event after Branch Device detection

Pass

(4.2.2.9)

E-DDC Four Block EDID Read

Skip

(4.3.1.1)

Successful Link Training Upon HPD Plug Event

Pass

(4.3.1.2)

Successful Link Training at All Supported Lane Counts and Link Speeds

Pass

(4.3.1.3)

Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence

Pass

(4.3.1.4)

Successful Link Training to a Lower Link Rate #1: Iterate at Maximum Voltage Swing

Skip

(4.3.1.5)

Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing

Skip

(4.3.1.6)

Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence

Fail

(4.3.1.7)

Successful Link Training at Lower Link Rate due to Loss of Symbol Lock During Channel Equalization Sequence

Pass

(4.3.1.8)

Unsuccessful Link Training at Lower Link Rate #1: Iterate at Maximum Voltage Swing

Fail

(4.3.1.9)

Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing

Fail

(4.3.1.10)

Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5)

Fail

(4.3.2.1)

Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock

Fail

(4.3.2.2)

Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock

Fail

(4.3.2.3)

Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock

Skip

(4.3.2.4)

Handling of IRQ HPD Pulse With No Error Status Bits Set

Fail

(4.3.2.5)

Lane Count Reduction

Skip

(4.3.2.6)

Lane Count Increase

Skip

(4.3.3.1)

Video Time Stamp Generation

Fail

(4.4.1.1)

Pixel Data Packing and Steering

Fail

(4.4.1.2)

Main Stream Data Packing and Stuffing ? Least Packed TU

Fail

(4.4.1.3)

Main Stream Data Packing and Stuffing ? Most Packed TU

Fail

(4.4.2)

Main Video Stream Format Change Handling

Skip

(4.4.3)

Power Management

Fail

     

Link Layer Extension Test Set A for Testing Transmitter DUT with DPR-120

Total:9/Pass:2/Fail: 7

Test Reference

Test Name

Result

(400.3.1.1)

Successful Link Training at All Supported Lane Counts and Link Speeds: HBR2 Extension

Pass

(400.3.1.2)

Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension

Pass

(400.3.1.3)

Successful Link Training to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

Fail

(400.3.1.4)

Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

Fail

(400.3.1.5)

Successful Link Training with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence

Fail

(400.3.1.6)

Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension

Fail

(400.3.1.7)

Unsuccessful Link Training at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

Fail

(400.3.1.8)

Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

Fail

(400.3.1.9)

Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5): HBR2 Extension

Fail

 

 

Best Regards~~

 

Open Source Technology Center (OTC)

Terence Yang（杨光）

Tel: 86-021-61167360

iNet: 8821-7360

 

 

 


<<< text/html; name="hsw25_dpr120_0415.HTM.html": Unrecognized >>>
Title: bdw01 Compliance Test Report

  DisplayPort Source Compliance Test Report

   Contents





View details by test
1 - (4.2.1.1) Source DUT Retry on No-Reply During Aux Read after Hot Plug Event 2 - (4.2.1.2) Source Retry on Invalid Reply During Aux Read after Hot Plug Event 3 - (4.2.2.1) EDID Read upon Hot Plug Event 4 - (4.2.2.2) DPCD Receiver Capability Read upon Hot Plug Event 5 - (4.2.2.3) EDID Read 6 - (4.2.2.4) EDID Read failure #1: I2C-Over-AUX NACK 7 - (4.2.2.5) EDID Read failure #2: I2C-Over-AUX DEFER 8 - (4.2.2.6) EDID Corruption Detection 9 - (4.2.2.7) Branch Device Detection upon HPD Plug Event 10 - (4.2.2.8) EDID read on IRQ_HPD event after Branch Device detection 11 - (4.2.2.9) E-DDC Four Block EDID Read 12 - (4.3.1.1) Successful Link Training Upon HPD Plug Event 13 - (4.3.1.2) Successful Link Training at All Supported Lane Counts and Link Speeds 14 - (4.3.1.3) Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence 15 - (4.3.1.4) Successful Link Training to a Lower Link Rate #1: Iterate at Maximum Voltage Swing 16 - (4.3.1.5) Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing 17 - (4.3.1.6) Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence 18 - (4.3.1.7) Successful Link Training at Lower Link Rate due to Loss of Symbol Lock During Channel Equalization Sequence 19 - (4.3.1.8) Unsuccessful Link Training at Lower Link Rate #1: Iterate at Maximum Voltage Swing 20 - (4.3.1.9) Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing 21 - (4.3.1.10) Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5) 22 - (4.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock 23 - (4.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock 24 - (4.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock 25 - (4.3.2.4) Handling of IRQ HPD Pulse With No Error Status Bits Set 26 - (4.3.2.5) Lane Count Reduction 27 - (4.3.2.6) Lane Count Increase 28 - (4.3.3.1) Video Time Stamp Generation 29 - (4.4.1.1) Pixel Data Packing and Steering 30 - (4.4.1.2) Main Stream Data Packing and Stuffing – Least Packed TU 31 - (4.4.1.3) Main Stream Data Packing and Stuffing – Most Packed TU 32 - (4.4.2) Main Video Stream Format Change Handling 33 - (4.4.3) Power Management 34 - (7.1.1.1) Additional DPCD Handling Test 1 35 - (7.1.1.2) Additional DPCD Handling Test 2

 

<<< text/html; name="bdw01_dpr120_0414.html": Unrecognized >>>
Title: Compliance Test Report

  DisplayPort Source Compliance Test Report

   Contents





View details by test
1 - (4.2.1.1) Source DUT Retry on No-Reply During Aux Read after Hot Plug Event 2 - (4.2.1.2) Source Retry on Invalid Reply During Aux Read after Hot Plug Event 3 - (4.2.2.1) EDID Read upon Hot Plug Event 4 - (4.2.2.2) DPCD Receiver Capability Read upon Hot Plug Event 5 - (4.2.2.3) EDID Read 6 - (4.2.2.4) EDID Read failure #1: I2C-Over-AUX NACK 7 - (4.2.2.5) EDID Read failure #2: I2C-Over-AUX DEFER 8 - (4.2.2.6) EDID Corruption Detection 9 - (4.2.2.7) Branch Device Detection upon HPD Plug Event 10 - (4.2.2.8) EDID read on IRQ_HPD event after Branch Device detection 11 - (4.2.2.9) E-DDC Four Block EDID Read 12 - (4.3.1.1) Successful Link Training Upon HPD Plug Event 13 - (4.3.1.2) Successful Link Training at All Supported Lane Counts and Link Speeds 14 - (4.3.1.3) Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence 15 - (4.3.1.4) Successful Link Training to a Lower Link Rate #1: Iterate at Maximum Voltage Swing 16 - (4.3.1.5) Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing 17 - (4.3.1.6) Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence 18 - (4.3.1.7) Successful Link Training at Lower Link Rate due to Loss of Symbol Lock During Channel Equalization Sequence 19 - (4.3.1.8) Unsuccessful Link Training at Lower Link Rate #1: Iterate at Maximum Voltage Swing 20 - (4.3.1.9) Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing 21 - (4.3.1.10) Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5) 22 - (4.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock 23 - (4.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock 24 - (4.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock 25 - (4.3.2.4) Handling of IRQ HPD Pulse With No Error Status Bits Set 26 - (4.3.2.5) Lane Count Reduction 27 - (4.3.2.6) Lane Count Increase 28 - (4.3.3.1) Video Time Stamp Generation 29 - (4.4.1.1) Pixel Data Packing and Steering 30 - (4.4.1.2) Main Stream Data Packing and Stuffing – Least Packed TU 31 - (4.4.1.3) Main Stream Data Packing and Stuffing – Most Packed TU 32 - (4.4.2) Main Video Stream Format Change Handling 33 - (4.4.3) Power Management 34 - (7.1.1.1) Additional DPCD Handling Test 1 35 - (7.1.1.2) Additional DPCD Handling Test 2

 

<<< text/html; name="byt01_dpr120_0415.HTM.html": Unrecognized >>>
Title: Compliance Test Report

  DisplayPort Source Compliance Test Report

   Contents





View details by test
1 - (4.2.1.1) Source DUT Retry on No-Reply During Aux Read after Hot Plug Event 2 - (4.2.1.2) Source Retry on Invalid Reply During Aux Read after Hot Plug Event 3 - (4.2.2.1) EDID Read upon Hot Plug Event 4 - (4.2.2.2) DPCD Receiver Capability Read upon Hot Plug Event 5 - (4.2.2.3) EDID Read 6 - (4.2.2.4) EDID Read failure #1: I2C-Over-AUX NACK 7 - (4.2.2.5) EDID Read failure #2: I2C-Over-AUX DEFER 8 - (4.2.2.6) EDID Corruption Detection 9 - (4.2.2.7) Branch Device Detection upon HPD Plug Event 10 - (4.2.2.8) EDID read on IRQ_HPD event after Branch Device detection 11 - (4.2.2.9) E-DDC Four Block EDID Read 12 - (4.3.1.1) Successful Link Training Upon HPD Plug Event 13 - (4.3.1.2) Successful Link Training at All Supported Lane Counts and Link Speeds 14 - (4.3.1.3) Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence 15 - (4.3.1.4) Successful Link Training to a Lower Link Rate #1: Iterate at Maximum Voltage Swing 16 - (4.3.1.5) Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing 17 - (4.3.1.6) Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence 18 - (4.3.1.7) Successful Link Training at Lower Link Rate due to Loss of Symbol Lock During Channel Equalization Sequence 19 - (4.3.1.8) Unsuccessful Link Training at Lower Link Rate #1: Iterate at Maximum Voltage Swing 20 - (4.3.1.9) Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing 21 - (4.3.1.10) Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5) 22 - (4.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock 23 - (4.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock 24 - (4.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock 25 - (4.3.2.4) Handling of IRQ HPD Pulse With No Error Status Bits Set 26 - (4.3.2.5) Lane Count Reduction 27 - (4.3.2.6) Lane Count Increase 28 - (4.3.3.1) Video Time Stamp Generation 29 - (4.4.1.1) Pixel Data Packing and Steering 30 - (4.4.1.2) Main Stream Data Packing and Stuffing – Least Packed TU 31 - (4.4.1.3) Main Stream Data Packing and Stuffing – Most Packed TU 32 - (4.4.2) Main Video Stream Format Change Handling 33 - (4.4.3) Power Management 34 - (7.1.1.1) Additional DPCD Handling Test 1 35 - (7.1.1.2) Additional DPCD Handling Test 2

  
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