On Tue, Apr 15, 2014 at 06:41:22PM +0200, Daniel Vetter wrote: > Like on hsw/bdw the pipe isn't actually running yet at this point. > This holds for both pch ports and the cpu edp port according to my > testing on ilk, snb and ivb. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77297 > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> Yeah I hate these weird waits we have sprinkled all over the place w/o clear justification. Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++---------- > 1 file changed, 4 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1aae7361b7a5..e0310e3018ee 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1827,16 +1827,6 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > > I915_WRITE(reg, val | PIPECONF_ENABLE); > POSTING_READ(reg); > - > - /* > - * There's no guarantee the pipe will really start running now. It > - * depends on the Gen, the output type and the relative order between > - * pipe and plane enabling. Avoid waiting on HSW+ since it's not > - * necessary. > - * TODO: audit the previous gens. > - */ > - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) > - intel_wait_for_vblank(dev_priv->dev, pipe); > } > > /** > @@ -4461,7 +4451,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) > > intel_update_watermarks(crtc); > intel_enable_pipe(intel_crtc); > + intel_wait_for_vblank(dev_priv->dev, pipe); > intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); > + > intel_enable_primary_hw_plane(dev_priv, plane, pipe); > intel_enable_planes(crtc); > intel_crtc_update_cursor(crtc, true); > @@ -4546,7 +4538,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) > > intel_update_watermarks(crtc); > intel_enable_pipe(intel_crtc); > + intel_wait_for_vblank(dev_priv->dev, pipe); > intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); > + > intel_enable_primary_hw_plane(dev_priv, plane, pipe); > intel_enable_planes(crtc); > /* The fixup needs to happen before cursor is enabled */ > -- > 1.8.4.rc3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
